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authorTomas Vanek <vanekt@fbl.cz>2020-10-22 13:18:40 +0200
committerAntonio Borneo <borneo.antonio@gmail.com>2020-11-15 21:08:56 +0000
commit608299484d52a60082bb7ff5bcde5249f9a3a1de (patch)
treefdeeed1c3a1be7487554b0f285e83a044040e712
parentf32ca2d25dae5526bf0bd70b1143aa34412fc7ec (diff)
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flash/nor/psoc6: remove setting of xPSR.T bit from sromalgo_prepare()
PSoC6 erases flash to 0x00 not more common 0xff, so a device with erased flash loads xPSR.T=0 from the zeroed reset vector. Wrong thumb bit value caused a target algorithm failed with HardFault. The low level write to xPSR solved the problem only if xPSR cached copy was not marked dirty. Later commit 49bd64347a21f5e12b33c256171b3035126d1260 fixed T setting for all Cortex-M target algorithms. Since 49bd64 this part of code is useless as xPSR target_start_algorithm() sets always xPSR dirty so the effect of the low level write is eliminated (and proper setting of thumb bit is ensured in target_start_algorithm()) Change-Id: I68aea5e921fbc6203f2fe91a45f10d22869327de Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/5875 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-rw-r--r--src/flash/nor/psoc6.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index 19d483b..931404e 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -151,12 +151,6 @@ static int sromalgo_prepare(struct target *target)
if (hr != ERROR_OK)
return hr;
- /* Restore THUMB bit in xPSR register */
- const struct armv7m_common *cm = target_to_armv7m(target);
- hr = cm->store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, 0x01000000);
- if (hr != ERROR_OK)
- return hr;
-
/* Allocate Working Area for Stack and Flash algorithm */
hr = target_alloc_working_area(target, RAM_STACK_WA_SIZE, &g_stack_area);
if (hr != ERROR_OK)