diff options
author | Tomas Vanek <vanekt@fbl.cz> | 2020-10-22 12:50:24 +0200 |
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committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-11-15 21:08:41 +0000 |
commit | f32ca2d25dae5526bf0bd70b1143aa34412fc7ec (patch) | |
tree | 03687b49529d5404dd4fafb2f71d53978b3caf51 | |
parent | fc91936be7bac7a84636d6b907ac545876263f3e (diff) | |
download | riscv-openocd-f32ca2d25dae5526bf0bd70b1143aa34412fc7ec.zip riscv-openocd-f32ca2d25dae5526bf0bd70b1143aa34412fc7ec.tar.gz riscv-openocd-f32ca2d25dae5526bf0bd70b1143aa34412fc7ec.tar.bz2 |
target/cortex_m: remove wrong xPSR.ICI/IT bits handling
If a Cortex-M (not M0, M0+) target was stopped in the middle of
a conditional IT block or in the load/store multiple instruction,
cortex_m_debug_entry() used wrong xPSR bits to detect it and then
cleared 8 bits of the exception number from xPSR
- probably wrong bit mask again.
I believe clearing of the ICI/IT bits in cortex_m_debug_entry() has no
reason as Cortex-M does not use instruction injecting.
Remove the wrong code.
The change was originally a part of http://openocd.zylin.com/4862
It is now re-submitted as #4862 is not ready.
Change-Id: If91cd91d1b81b2684f7d5f10cf20452cde1a7f56
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5874
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
-rw-r--r-- | src/target/cortex_m.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index 7b3f3c7..fc72c0e 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -527,12 +527,6 @@ static int cortex_m_debug_entry(struct target *target) r = arm->cpsr; xPSR = buf_get_u32(r->value, 0, 32); - /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */ - if (xPSR & 0xf00) { - r->dirty = r->valid; - cortex_m_store_core_reg_u32(target, ARMV7M_REGSEL_xPSR, xPSR & ~0xff); - } - /* Are we in an exception handler */ if (xPSR & 0x1FF) { armv7m->exception_number = (xPSR & 0x1FF); |