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| author | Tim Newsome <tim@sifive.com> | 2023-04-05 14:57:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-04-05 14:57:57 -0700 |
| commit | 21d2787d64952c7d794591ccda40edd21cab9cf1 (patch) | |
| tree | 6e9468cb2871e8a127ee2d1078a4787bc463bf6f | |
| parent | c6ba4166e47c3bc319babfabac9227e2db7ac7d5 (diff) | |
| parent | 7e36bb615837f53bd4c720451e057e3b7d4745b3 (diff) | |
| download | riscv-openocd-21d2787d64952c7d794591ccda40edd21cab9cf1.zip riscv-openocd-21d2787d64952c7d794591ccda40edd21cab9cf1.tar.gz riscv-openocd-21d2787d64952c7d794591ccda40edd21cab9cf1.tar.bz2 | |
Merge pull request #825 from riscv/hypervisor
target/riscv: Set hypervisor bits.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 | ||||
| -rw-r--r-- | src/target/riscv/riscv.c | 10 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 35fc27e..e11265b 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -4547,6 +4547,8 @@ static int riscv013_on_step_or_resume(struct target *target, bool step) dcsr = set_field(dcsr, CSR_DCSR_EBREAKM, riscv_ebreakm); dcsr = set_field(dcsr, CSR_DCSR_EBREAKS, riscv_ebreaks); dcsr = set_field(dcsr, CSR_DCSR_EBREAKU, riscv_ebreaku); + dcsr = set_field(dcsr, CSR_DCSR_EBREAKVS, riscv_ebreaku); + dcsr = set_field(dcsr, CSR_DCSR_EBREAKVU, riscv_ebreaku); if (riscv_set_register(target, GDB_REGNO_DCSR, dcsr) != ERROR_OK) return ERROR_FAIL; if (riscv_flush_registers(target) != ERROR_OK) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index a5cdda5..9322728 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -736,7 +736,9 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2( static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6( struct target *target, struct trigger *trigger) { - RISCV_INFO(r); + bool misa_s = riscv_supports_extension(target, 'S'); + bool misa_u = riscv_supports_extension(target, 'U'); + bool misa_h = riscv_supports_extension(target, 'H'); struct match_triggers_tdata1_fields result = { .common = @@ -744,8 +746,10 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6( field_value(CSR_MCONTROL6_DMODE(riscv_xlen(target)), 1) | field_value(CSR_MCONTROL6_ACTION, CSR_MCONTROL_ACTION_DEBUG_MODE) | field_value(CSR_MCONTROL6_M, 1) | - field_value(CSR_MCONTROL6_S, !!(r->misa & BIT('S' - 'A'))) | - field_value(CSR_MCONTROL6_U, !!(r->misa & BIT('U' - 'A'))) | + field_value(CSR_MCONTROL6_S, misa_s) | + field_value(CSR_MCONTROL6_U, misa_u) | + field_value(CSR_MCONTROL6_VS, misa_h && misa_s) | + field_value(CSR_MCONTROL6_VU, misa_h && misa_u) | field_value(CSR_MCONTROL6_EXECUTE, trigger->is_execute) | field_value(CSR_MCONTROL6_LOAD, trigger->is_read) | field_value(CSR_MCONTROL6_STORE, trigger->is_write), |