From 4fdcc14e2645252916cc2e8467ff5ce95f4795dc Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Fri, 24 Mar 2023 13:16:54 -0700 Subject: target/riscv: Set hypervisor bits. No other attempt is made at doing anything hypervisor-specific. Are other things necessary? Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f Signed-off-by: Tim Newsome --- src/target/riscv/riscv-013.c | 2 ++ src/target/riscv/riscv.c | 10 +++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index e15384a..dd97496 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -4531,6 +4531,8 @@ static int riscv013_on_step_or_resume(struct target *target, bool step) dcsr = set_field(dcsr, CSR_DCSR_EBREAKM, riscv_ebreakm); dcsr = set_field(dcsr, CSR_DCSR_EBREAKS, riscv_ebreaks); dcsr = set_field(dcsr, CSR_DCSR_EBREAKU, riscv_ebreaku); + dcsr = set_field(dcsr, CSR_DCSR_EBREAKVS, riscv_ebreaku); + dcsr = set_field(dcsr, CSR_DCSR_EBREAKVU, riscv_ebreaku); if (riscv_set_register(target, GDB_REGNO_DCSR, dcsr) != ERROR_OK) return ERROR_FAIL; if (riscv_flush_registers(target) != ERROR_OK) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 3c91526..e9a817c 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -732,7 +732,9 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2( static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6( struct target *target, struct trigger *trigger) { - RISCV_INFO(r); + bool misa_s = riscv_supports_extension(target, 'S'); + bool misa_u = riscv_supports_extension(target, 'U'); + bool misa_h = riscv_supports_extension(target, 'H'); struct match_triggers_tdata1_fields result = { .common = @@ -740,8 +742,10 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6( field_value(CSR_MCONTROL6_DMODE(riscv_xlen(target)), 1) | field_value(CSR_MCONTROL6_ACTION, CSR_MCONTROL_ACTION_DEBUG_MODE) | field_value(CSR_MCONTROL6_M, 1) | - field_value(CSR_MCONTROL6_S, !!(r->misa & BIT('S' - 'A'))) | - field_value(CSR_MCONTROL6_U, !!(r->misa & BIT('U' - 'A'))) | + field_value(CSR_MCONTROL6_S, misa_s) | + field_value(CSR_MCONTROL6_U, misa_u) | + field_value(CSR_MCONTROL6_VS, misa_h && misa_s) | + field_value(CSR_MCONTROL6_VU, misa_h && misa_u) | field_value(CSR_MCONTROL6_EXECUTE, trigger->execute) | field_value(CSR_MCONTROL6_LOAD, trigger->read) | field_value(CSR_MCONTROL6_STORE, trigger->write), -- cgit v1.1