| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 26 hours | Fix definition of mcontrol.action | YenHaoChen | 1 | -1/+1 | |
| 12 days | Add extended cause codes in DCSR | Ved Shanbhogue | 1 | -0/+3 | |
| 2024-07-01 | Add pointer masking related CSR fields (#256) | YenHaoChen | 1 | -0/+5 | |
| 2024-06-04 | Fix typo in CTR bitfield definition (#253) | Ved Shanbhogue | 1 | -2/+2 | |
| 2024-06-04 | Add unratified Smctr/Ssctr instructions and CSRs (#252) | Ved Shanbhogue | 1 | -0/+71 | |
| 2024-05-05 | Add unratified Ssdbltrp and Smdbltrp fields (#238) | Ved Shanbhogue | 1 | -7/+18 | |
| * Add Ssdbltrp, Smdbltrp, and Sddbltrp fields * Add Ssdbltrp, Smdbltrp, and Sddbltrp fields * renasme pcerr to cetrig; fix fields of dcsr to match 1.0 spec | |||||
| 2024-05-01 | Add shadow stack fault code | Andrew Waterman | 1 | -0/+1 | |
| 2024-04-10 | Add mstateen0[60] for Smcsrind/Sscsrind (#241) | YenHaoChen | 1 | -0/+4 | |
| Signed-off-by: Andrew Waterman <andrew@sifive.com> Co-authored-by: Andrew Waterman <andrew@sifive.com> | |||||
| 2024-04-10 | Add stateen0[59] for AIA (#242) | YenHaoChen | 1 | -0/+4 | |
| 2024-02-26 | Add definition of low-priority and high-priority RAS event from AIA (#234) | YenHaoChen | 1 | -15/+19 | |
| 2024-02-21 | Add CSR fields of mtopi | YenHaoChen | 1 | -0/+3 | |
| 2024-02-18 | Remove erroneous MSTATEEN0[H]_HENVCFGH macros (#230) | Andrew Waterman | 1 | -2/+0 | |
| MSTATEEN0[H]_HENVCFG should be used instead. Resolves #229 | |||||
| 2024-02-15 | Add CSR fields of hvictl (#228) | YenHaoChen | 1 | -0/+6 | |
| 2024-02-03 | Add Zicfilp codes (#225) | mylai-mtk | 1 | -0/+3 | |
| 2023-12-25 | update mstateen0 fields (#218) | Ved Shanbhogue | 1 | -1/+4 | |
| 2023-12-23 | add srmcfg CSR | Ved Shanbhogue | 1 | -0/+4 | |
| 2023-11-27 | CSR fields introduced by Zicfilp (#210) | Ved Shanbhogue | 1 | -0/+8 | |
| 2023-11-24 | CSR fields introduced by Zicfiss | Ved Shanbhogue | 1 | -0/+3 | |
| 2023-08-13 | Svadu: Rename HADE to ADUE | Ved Shanbhogue | 1 | -4/+4 | |
| 2023-07-12 | Add Smcdeleg CSR+constants | Atul Khare | 1 | -0/+13 | |
| Adds CSR scountinhibit (0x120), MSTATEEN0.CD (bit 56), and siselect range (0x40 - 0x5F). | |||||
| 2023-03-16 | Add Snrmni CSR and field definitions | Andrew Waterman | 1 | -0/+4 | |
| 2023-01-26 | Add support for Svadu | Aaron Durbin | 1 | -0/+4 | |
| The Svadu extension (https://github.com/riscv/riscv-svadu) adds the HADE bit (61) to menvcfg and henvcfg CSRs to control updating of the A/D bits in the PTE. Provide the bit encodings for the HADE support. | |||||
| 2022-11-17 | Add support for Zc* extensions (#107) | liweiwei90 | 1 | -0/+7 | |
| 2022-07-22 | Move the SPDX tag to the first line (#137) | Antonio Borneo | 1 | -2/+0 | |
| Linux kernel coding style requires the SPDX tag to be placed in the very first line of the generated file. See kernel file Documentation/process/license-rules.rst at chapter 'License identifier syntax', '1. Placement:'. Move the SPDX tag in the python script. While there, adjust also the style of the multi-line comment. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> | |||||
| 2022-07-06 | Remove UCB HTIF-specific interrupt from encoding.h | Andrew Waterman | 1 | -1/+0 | |
| 2022-07-04 | add field definition for MIP/SIP csrs added by Sscofpmf extension | Weiwei Li | 1 | -0/+2 | |
| 2022-07-04 | add field definition for mhpmevent csrs added by Sscofpmf extension | Weiwei Li | 1 | -0/+14 | |
| 2022-07-02 | add field definition for stateen csrs | Weiwei Li | 1 | -0/+23 | |
| 2022-06-30 | Change license to BSD-3-Clause-Clear (#133) | Tim Newsome | 1 | -1/+1 | |
| Previously the license was a hybrid between the conditions form BSD-3-Clause-Clear and the disclaimer from MIT-Modern-Variant. Using a standard license makes it easier to include the generated code into other open source projects. | |||||
| 2022-03-28 | Define HGATP_MODE_SV57X4 for Sv57x4 translation mode | Andrew Waterman | 1 | -0/+1 | |
| 2021-12-16 | Add new CSR bits defined in Privileged Spec version 1.12 (#94) | Tsukasa #01 (a4lg) | 1 | -0/+31 | |
| 2021-11-02 | Remove no-longer-used SSTATUS_VS_MASK | Scott Johnson | 1 | -4/+0 | |
| Spike removed this in https://github.com/riscv-software-src/riscv-isa-sim/commit/60243a3bf9f86de5b8b58807ae218f1e3aedc31c I checked other uses of encoding.h (riscv-pk, riscv-test-env, riscv-openocd), and confirmed that none of them use this value. | |||||
| 2021-11-02 | Add new hypervisor bits to mstatush | Scott Johnson | 1 | -0/+2 | |
| In Spike, I added these by hand in https://github.com/riscv-software-src/riscv-isa-sim/commit/4730be82e63ec8bf4a30aa59afee5e5b58a0fbe4 | |||||
| 2021-07-19 | Virtual memory updates (#76) | Daniel Lustig | 1 | -0/+3 | |
| * Add Svinval instructions * Add PTE defines for Priv 1.12 and Svpbmt | |||||
| 2021-06-07 | Update PTE_N encoding | Andrew Waterman | 1 | -1/+1 | |
| See https://github.com/riscv/riscv-isa-sim/pull/724 | |||||
| 2021-01-23 | Removing platform-specific definitions (#59) | Dan Petrisko | 1 | -6/+0 | |
| 2021-01-08 | Add Zsn to encoding.h | Andrew Waterman | 1 | -0/+1 | |
| 2021-01-08 | Update mstatus/sstatus fields for hypervisor v0.6 | Andrew Waterman | 1 | -2/+8 | |
| 2020-07-31 | hyperviosr: add csr mask and interrupt macro name | Chih-Min Chao | 1 | -7/+46 | |
| This part copy the implementation which has been merged in spike Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2020-05-04 | Add DCSR_CAUSE_GROUP. (#44) | Tim Newsome | 1 | -0/+1 | |
| 2020-02-24 | Add N-extension CSRs and status bits. (#37) | michael-roe | 1 | -0/+9 | |
| 2020-02-13 | Remove mstatus.HPP; move mstatus.VS to its old location | Andrew Waterman | 1 | -3/+2 | |
| See https://github.com/riscv/riscv-v-spec/pull/351 | |||||
| 2019-11-28 | rvv: add vleb csr register and mstatus.vs field | Chih-Min Chao | 1 | -0/+2 | |
| 1. vleb is read-only CSR to keep vector implementation lenght in byte 2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension state Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
| 2017-12-27 | Use old C style comments. (#18) | Tim Newsome | 1 | -11/+11 | |
| This improves the chance we can use this file with older, pickier compilers. Also it makes the OpenOCD patch check script happier. | |||||
| 2017-11-27 | Rename sptbr to satp and sbadaddr to stval | Andrew Waterman | 1 | -15/+15 | |
| Closes #17 | |||||
| 2017-05-07 | Add UXl/SXL | Andrew Waterman | 1 | -0/+3 | |
| 2017-03-30 | New PMP encoding | Andrew Waterman | 1 | -5/+6 | |
| 2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -3/+2 | |
| 2017-03-23 | Add PMP | Andrew Waterman | 1 | -1/+12 | |
| 2017-03-23 | Add TW/TVM/TSR fields to mstatus | Andrew Waterman | 1 | -1/+4 | |
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index : riscv-tools/riscv-opcodes.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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path: root/encoding.h