aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
8 hoursInclude rs1 values in Go instruction opcodes. (#254)HEADmasterJoel Sing1-1/+3
Some of the instructions in the V extension encode part of the opcode in the rs1 field. These values are not currently included in the Go instruction opcodes - fix this by adding an rs1 field and populating it with the relevant values.
2024-06-04Fix typo in CTR bitfield definition (#253)Ved Shanbhogue1-2/+2
2024-06-04Add unratified Smctr/Ssctr instructions and CSRs (#252)Ved Shanbhogue3-0/+77
2024-05-28Update rv_v to fix typo (#251)Pengcheng Wang1-1/+1
Signed-off-by: Pengcheng Wang <wangpengcheng.pp@bytedance.com>
2024-05-15Fix typos in parse.py (#247)Patrick Yingxi Pan1-3/+3
Signed-off-by: Patrick Yingxi Pan <patrick-yingxi-pan@users.noreply.github.com>
2024-05-05Add unratified Ssdbltrp and Smdbltrp fields (#238)Ved Shanbhogue1-7/+18
* Add Ssdbltrp, Smdbltrp, and Sddbltrp fields * Add Ssdbltrp, Smdbltrp, and Sddbltrp fields * renasme pcerr to cetrig; fix fields of dcsr to match 1.0 spec
2024-05-05Mark Zihintntl, Zicond, Zfa, Zbkb, and Zvbc as ratified (#246)Ved Shanbhogue24-29/+22
* Mark Zihintntl as ratified * Mark Zicond as ratified * Mark Zfa as ratified * Mark Zvbc as ratified * Mark Zbkb ratified * Mark xperm4/8 of Zbkx as ratified * Update Zbkb - remove Zbe
2024-05-05Mark Zimop and Zcmop ratified (#245)Ved Shanbhogue2-0/+0
2024-05-05Mark Zabha ratified (#244)Ved Shanbhogue1-0/+0
2024-05-01Remove remainder of B extensionsAndrew Waterman2-21/+0
Continuation of f0c6e9575f640e31a591b03f6bced408e9e08bac
2024-05-01Remove remainder of P extensionsAndrew Waterman2-39/+0
Continuation of e07ce62356e1f9a4497ec004fda5e6d5aadfcd48
2024-05-01Add shadow stack fault codeAndrew Waterman1-0/+1
2024-05-01Remove legacy bit-manipulation extensionsAndrew Waterman12-65/+0
These do not have a path to ratification. I left the ones that are generic versions of ratified instructions (e.g. orc.b is a special case of gorci).
2024-05-01Remove old P extensionsAndrew Waterman6-293/+0
See https://github.com/riscv-software-src/riscv-isa-sim/pull/1660 for explanation
2024-05-01Remove unratified vector memory-access instructionsAndrew Waterman1-36/+0
ELEN > 64 was not actually defined and ratified. These were just hypothetical encodings.
2024-05-01Correctly detect overlapping encodingsAndrew Waterman2-11/+48
A regression introduced a few years ago prevented detecting partially overlapping encodings; instead, we only detected exact matches. Now, we detect the partial cases. We now need to maintain two allowlists (overlapping_extensions and overlapping_instructions) for the cases that extensions and/or instructions overlap by design.
2024-05-01Remove RV128 for nowAndrew Waterman4-44/+1
It is highly speculative at this point, but it adds maintenance burden.
2024-05-01Remove legacy bitmanip encodings that are now conflictingAndrew Waterman2-8/+0
Zbt (cmov) conflicts with ratified Zicond (czero.eqz) Zbm will conflict with soon-to-be-frozen Zpa
2024-04-10Add mstateen0[60] for Smcsrind/Sscsrind (#241)YenHaoChen1-0/+4
Signed-off-by: Andrew Waterman <andrew@sifive.com> Co-authored-by: Andrew Waterman <andrew@sifive.com>
2024-04-10Add stateen0[59] for AIA (#242)YenHaoChen1-0/+4
2024-03-01move opcode of zvb* (#236)Lucas9-0/+0
* move opcode of zvbb * move all zvk* out
2024-02-26Add definition of low-priority and high-priority RAS event from AIA (#234)YenHaoChen1-15/+19
2024-02-21Merge pull request #232 from YenHaoChen/pr-mtopiNeel Gala1-0/+3
Add CSR fields of mtopi
2024-02-21Add CSR fields of mtopiYenHaoChen1-0/+3
2024-02-18Remove erroneous MSTATEEN0[H]_HENVCFGH macros (#230)Andrew Waterman1-2/+0
MSTATEEN0[H]_HENVCFG should be used instead. Resolves #229
2024-02-15Add CSR fields of hvictl (#228)YenHaoChen1-0/+6
2024-02-12Made Typo correction in READ.MD (#223) (#227)akshaykumars6141-1/+1
2024-02-03Add Zicfilp codes (#225)mylai-mtk3-0/+6
2024-01-08Add `.rv32` on rv32_zbs and rv32_zbb instructions (#220)hirooih7-15/+22
* Add .rv32 on rv32_zbs instructions to be consistent with slli, srli, and srai. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> * Add .rv32 on rv32_zbb instructions - zext.h.rv32, rev8.rv32, and rori.rev32 - rev8.rv32, and rori.rev32 are also aliased in rv32_{zk,zkn,zks,zbkb} - only rv32_zks is shown in the extension field Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com> --------- Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
2024-01-08Add missing `-n0` (#219)hirooih2-4/+4
add `_n0' on `rd` for `c.li`, `c.mv`, `c.add`, and `c.lqsp`. Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
2023-12-25update mstateen0 fields (#218)Ved Shanbhogue1-1/+4
2023-12-23Merge pull request #216 from ved-rivos/ssqosidAndrew Waterman2-0/+5
Add unratified srmcfg CSR
2023-12-23Merge pull request #217 from ved-rivos/zacas_ratifiedAndrew Waterman2-0/+0
Update Zacas as ratified
2023-12-23mark zacas ratifiedVed Shanbhogue2-0/+0
2023-12-23add srmcfg CSRVed Shanbhogue2-0/+5
2023-11-27Merge pull request #212 from ved-rivos/sw_check_exceptionAndrew Waterman1-0/+2
Add software check and hardware error faults
2023-11-27Merge pull request #211 from ved-rivos/zicfiss_instsAndrew Waterman3-0/+26
Add unratified Zicfiss extension instructions
2023-11-27CSR fields introduced by Zicfilp (#210)Ved Shanbhogue1-0/+8
2023-11-25add software check and hardware error faultsVed Shanbhogue1-0/+2
2023-11-25add zicfiss instructionsVed Shanbhogue1-0/+14
2023-11-25add compressed zicfiss instructionsVed Shanbhogue1-0/+5
2023-11-25add pseudoops for zicfiss instsVed Shanbhogue1-0/+7
2023-11-24Merge pull request #209 from ved-rivos/zicfissAndrew Waterman2-0/+4
Add CSR fields and SSP CSR introduced by unratified Zicfiss extension
2023-11-24SSP CSR introduced by ZicfissVed Shanbhogue1-0/+1
2023-11-24CSR fields introduced by ZicfissVed Shanbhogue1-0/+3
2023-11-01Merge pull request #206 from ved-rivos/zabhaAndrew Waterman1-0/+23
Add unratified Zabha extension
2023-10-29Add Zabha AMO inst code pointsVed Shanbhogue1-0/+23
2023-10-26Merge pull request #205 from tomhepworth/masterAndrew Waterman1-1/+3
Clarified syntax of regular instructions
2023-10-26Clarified syntax of regular instructionsThomas Hepworth1-1/+3
See https://github.com/riscv/riscv-opcodes/issues/204 Before this change the text implied that bit encodings and variable arguments could not be mixed in the list of instruction arguments. Signed-off-by: Thomas Hepworth <tomhepworth@hotmail.co.uk>
2023-10-20Merge pull request #201 from mehnadnerd/masterAndrew Waterman1-0/+8
Adding Zalasr
generated by cgit v1.1 at 2024-06-28 04:50:50 +0000