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AgeCommit message (Expand)AuthorFilesLines
2019-05-16Cover with/without halt groups. (#191)Tim Newsome4-5/+6
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome6-6/+9
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome4-5/+11
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome3-0/+57
2018-12-31Add testing of run-test/idle cases.Tim Newsome6-6/+7
2018-11-14Merge pull request #165 from riscv/flashTim Newsome2-0/+59
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv2-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv2-2/+4
2018-10-31Add HiFive1-flash target configuration.Tim Newsome2-0/+59
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome9-0/+9
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome3-3/+18
2018-03-01Test debugging with/without a program bufferTim Newsome3-3/+3
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome4-0/+16
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome9-4/+48
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome2-2/+2
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
2017-08-28Make pylint happy.Tim Newsome3-3/+3
2017-08-28WIP multicore testing.Tim Newsome4-0/+8
2017-08-28Make the debug tests aware of multicore.Tim Newsome11-38/+63
2017-08-10Give these sim targets a chance of passing.Tim Newsome2-3/+7
2017-06-26Move target definition into individual files.Tim Newsome21-148/+74
2017-06-15Test 64-bit addressing.Tim Newsome4-0/+53
2017-06-09Add final echo to E300/U500 OpenOCD scriptsTim Newsome2-0/+2
2017-06-09Make HiFive1 testing (mostly) work againTim Newsome2-2/+5
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt1-1/+1
2017-05-16debug: Update OpenOCD configs.Megan Wachs2-5/+4
2017-05-15Don't use the RTOS, and do "reset halt"Palmer Dabbelt1-3/+4
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops (...Megan Wachs1-1/+2
2017-04-18debug: Use RTOS OpenOCD for Spike for now.Megan Wachs1-1/+1
2017-04-17Merge remote-tracking branch 'origin/newprogram' into debug-0.13Megan Wachs5-7/+10
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs5-5/+5
2017-04-14debug: checkpoint of trying to get simulation tests workingMegan Wachs5-5/+7
2017-04-14debug: working with newprogram branchMegan Wachs2-3/+4
2017-03-29Change the global pointer symbol to __global_pointer$Palmer Dabbelt5-5/+5
2017-03-03Resurrect spike debug supportPalmer Dabbelt1-0/+17
2017-02-17Add HiFive1 target.Tim Newsome2-0/+57
2016-10-18Pull port number from VCS output and pass to OpenOCD.Richard Xia2-0/+2
2016-10-03Add test for memory read from invalid address.Tim Newsome1-0/+2
2016-08-11Add FreedomU500 & incorporate feedbackMegan Wachs5-18/+47
2016-08-08Add U500 TargetMegan Wachs2-0/+53
2016-08-08Added FreedomE300 Simulator targetMegan Wachs2-0/+53
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