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path: root/debug/gdbserver.py
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2020-02-14Add tests for vector register access (#244)Tim Newsome1-0/+21
2020-02-11Generate very different values on different harts. (#238)Tim Newsome1-4/+4
2020-02-11Look for \bmain\b instead of ' main '. (#237)Tim Newsome1-2/+2
2020-01-15Force DMI busy in all tests. (#235)Tim Newsome1-9/+26
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome1-0/+49
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome1-0/+8
2019-11-22Move to Python 3. (#218)Tim Newsome1-34/+36
2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome1-2/+4
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-8/+7
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome1-1/+4
2019-06-14Work better with mainline gdb (#192)Tim Newsome1-8/+8
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome1-8/+13
2019-03-11Add SmpSimultaneousRunHalt test. (#181)Tim Newsome1-0/+49
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome1-10/+12
2019-01-07Fail on unsupported SREC type.Tim Newsome1-0/+2
2018-12-31Fix MemTestBlockTim Newsome1-20/+41
2018-12-03Reduce download size a bit.Tim Newsome1-4/+8
2018-11-30Use more than 1KB for download test.Tim Newsome1-1/+1
2018-11-16Make pylint happy.Tim Newsome1-3/+6
2018-11-14Merge pull request #165 from riscv/flashTim Newsome1-13/+33
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv1-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv1-0/+52
2018-10-31Fix remaining tests to work from flash:Tim Newsome1-4/+12
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome1-3/+12
2018-10-29Tweak debug tests to run out of flash.Tim Newsome1-6/+9
2018-10-24Merge branch 'TriggerLoadAddressInstant'Tim Newsome1-12/+1
2018-10-24Re-enable TriggerStoreAddressInstantTim Newsome1-12/+1
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome1-5/+8
2018-10-03Added tests for hw and sw watchpointscgsfv1-0/+56
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
2018-08-31Fix CustomRegisterTest.Tim Newsome1-1/+2
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+30
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome1-2/+3
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
2018-08-22Add debug test, which checks that openocd correctly switch active thread on a...Dmitry Ryzhov1-0/+28
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome1-19/+37
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs1-17/+4
2018-05-14Make DownloadTest properly park other harts.Tim Newsome1-1/+2
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
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