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2019-07-01pmp: first set the address, then cfg (#194)Pentin Alexander Sergeevich1-1/+1
2019-06-14Work better with mainline gdb (#192)Tim Newsome2-23/+46
* Parse floats the way mainline gdb prints them. For 64-bit floats, it shows both float and double results. Now more tests pass using mainline gdb. * Disable ANSI when talking to gdb. Helps more tests pass with mainline gdb. * Parse {float=...,double=...} in "info registers" Makes tests work better with mainline gdb.
2019-05-16Cover with/without halt groups. (#191)Tim Newsome5-12/+20
Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-20Merge branch 'neelgala-master'Andrew Waterman1-19/+4
2019-04-20masking no longer required.Neel1-16/+0
2019-04-20removing check for reset value of type in mcontrolNeel1-10/+8
2019-04-20fix for #159 #158Neel1-4/+7
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome7-8/+14
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome9-31/+51
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-03-17Rename TEST_SRL to TEST_SRLI to avoid conflicts with another TEST_SRL (#183)Pavel I. Kryukov1-18/+18
2019-03-11Add SmpSimultaneousRunHalt test. (#181)Tim Newsome4-10/+89
This test confirms that in SMP configurations OpenOCD halts the harts near-simulatenously. (It'll also check for resume, but that's not implemented yet so commented out for now.)
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome6-22/+81
* WIP * Use hwthread everywhere. * Test `-rtos hwthread`. Also tweak timeouts a bit so that we don't have ridiculous timeouts for simple operations. * Tweak timeouts so tests pass on a loaded system.
2019-01-26Fix comments for shift amount. (#177)takeoverjp3-3/+3
2019-01-25Merge pull request #175 from riscv/test_rtiCarsten Gosvig7-7/+17
Add testing of run-test/idle cases.
2019-01-07Merge pull request #174 from riscv/MemTestBlockTim Newsome1-20/+43
Fix MemTestBlock
2019-01-07Fail on unsupported SREC type.Tim Newsome1-0/+2
2019-01-04bump envAndrew Waterman1-5/+5
2018-12-31Add testing of run-test/idle cases.Tim Newsome7-7/+17
2018-12-31Fix MemTestBlockTim Newsome1-20/+41
This test used to false pass on 64-bit targets because gdb doesn't like using Intel hex files on 64-bit targets.
2018-12-18Avoid using t3 and t4 for supporting RV32E (#173)zhonghochen1-5/+6
2018-12-03Reduce download size a bit.Tim Newsome2-6/+9
Increase some timeouts in case memory access is slow.
2018-12-03Merge pull request #172 from riscv/downloadtestTim Newsome1-1/+1
Use more than 1KB for download test.
2018-11-30Use more than 1KB for download test.Tim Newsome1-1/+1
This is a pretty old bug. I limited the size to 256KB because against spike my machine gets about 8KB/s, and I don't want to wait forever for `make` to pass.
2018-11-16Make pylint happy.Tim Newsome1-3/+6
2018-11-16Test memory content on failing SC (#171)Florian Zaruba1-4/+10
2018-11-14Merge pull request #165 from riscv/flashTim Newsome7-18/+103
Tweak debug tests to run out of flash.
2018-11-14Merge pull request #169 from riscv/eclipse_memory_readCarsten Gosvig4-2/+59
Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv4-6/+6
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv4-2/+59
2018-11-12Simpler/more idiomatic way to keep string on stackTim Newsome1-4/+1
2018-10-31Add HiFive1-flash target configuration.Tim Newsome2-0/+59
2018-10-31Fix remaining tests to work from flash:Tim Newsome2-6/+17
TriggerDmode, ProgramHwWatchpoint, ProgramSwWatchpoint.
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome2-4/+13
Only TriggerDmode still fails.
2018-10-29Tweak debug tests to run out of flash.Tim Newsome4-8/+17
Not all tests pass when run out of flash yet, but it's getting a lot closer. The ones still failing on HiFive1-flash are: DebugSymbols, Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and TriggerStoreAddressInstant.
2018-10-24Merge branch 'TriggerLoadAddressInstant'Tim Newsome1-12/+1
2018-10-24Re-enable TriggerStoreAddressInstantTim Newsome1-12/+1
Gdb and OpenOCD were fixed so we don't have to accept broken behavior anymore.
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome3-7/+10
Also tiny cleanups, making pylint happy.
2018-10-03Added tests for hw and sw watchpointscgsfv3-0/+88
2018-09-23bump envAndrew Waterman1-5/+5
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-09-08Merge branch 'tommythorn-master'Andrew Waterman6-0/+42
2018-09-08RV64 s{ll,ra,rl}w tests with non-canonical valuesTommy Thorn6-0/+42
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵Andrew Waterman1-1/+1
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158.
2018-09-06breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)Tommy Thorn1-1/+1
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
Reset address translation/perms before PrivChange
2018-08-31Fix CustomRegisterTest.Tim Newsome2-5/+6
gdb in riscv-tools doesn't automatically create a "custom" group like mainline gdb does.
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome12-0/+55
Only works against spike, where I've implemented some custom debug registers to test against.
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
We already did this for PrivTest. Hopefully solves #155, but I haven't been able to reproduce it.
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful.
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