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| author | Andrew Waterman <andrew@sifive.com> | 2018-09-08 15:10:44 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2018-09-08 15:10:44 -0700 |
| commit | 0c0d77c594305417cd8305e17950f86da14e71c4 (patch) | |
| tree | 1f9a771dd305e03bd4b6efee92c50952f01c4524 | |
| parent | 9d3bc86d85d935f498065d54ead7e568f03b2824 (diff) | |
| parent | ab4f35d0300e5dcfc62837d79b0c59d309f2ebfc (diff) | |
| download | riscv-tests-0c0d77c594305417cd8305e17950f86da14e71c4.zip riscv-tests-0c0d77c594305417cd8305e17950f86da14e71c4.tar.gz riscv-tests-0c0d77c594305417cd8305e17950f86da14e71c4.tar.bz2 | |
Merge branch 'tommythorn-master'
| -rw-r--r-- | isa/rv64ui/slliw.S | 7 | ||||
| -rw-r--r-- | isa/rv64ui/sllw.S | 7 | ||||
| -rw-r--r-- | isa/rv64ui/sraiw.S | 7 | ||||
| -rw-r--r-- | isa/rv64ui/sraw.S | 7 | ||||
| -rw-r--r-- | isa/rv64ui/srliw.S | 7 | ||||
| -rw-r--r-- | isa/rv64ui/srlw.S | 7 |
6 files changed, 42 insertions, 0 deletions
diff --git a/isa/rv64ui/slliw.S b/isa/rv64ui/slliw.S index 7822f09..0ed888b 100644 --- a/isa/rv64ui/slliw.S +++ b/isa/rv64ui/slliw.S @@ -35,6 +35,13 @@ RVTEST_CODE_BEGIN TEST_IMM_OP( 15, slliw, 0x0000000048484000, 0x0000000021212121, 14 ); TEST_IMM_OP( 16, slliw, 0xffffffff80000000, 0x0000000021212121, 31 ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, slliw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, slliw, 0x0000000023456780, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, slliw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, slliw, 0xffffffff93456780, 0x0000000099345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- diff --git a/isa/rv64ui/sllw.S b/isa/rv64ui/sllw.S index 59770ee..62b4db6 100644 --- a/isa/rv64ui/sllw.S +++ b/isa/rv64ui/sllw.S @@ -43,6 +43,13 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 20, sllw, 0x0000000048484000, 0x0000000021212121, 0xffffffffffffffee ); TEST_RR_OP( 21, sllw, 0xffffffff80000000, 0x0000000021212121, 0xffffffffffffffff ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, sllw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, sllw, 0x0000000023456780, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, sllw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, sllw, 0xffffffff93456780, 0x0000000099345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- diff --git a/isa/rv64ui/sraiw.S b/isa/rv64ui/sraiw.S index 9240c9b..a435e59 100644 --- a/isa/rv64ui/sraiw.S +++ b/isa/rv64ui/sraiw.S @@ -35,6 +35,13 @@ RVTEST_CODE_BEGIN TEST_IMM_OP( 15, sraiw, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); TEST_IMM_OP( 16, sraiw, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, sraiw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, sraiw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, sraiw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, sraiw, 0xfffffffff9234567, 0x0000000092345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- diff --git a/isa/rv64ui/sraw.S b/isa/rv64ui/sraw.S index 8c234c1..68d913e 100644 --- a/isa/rv64ui/sraw.S +++ b/isa/rv64ui/sraw.S @@ -43,6 +43,13 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 20, sraw, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffee ); TEST_RR_OP( 21, sraw, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, sraw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, sraw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, sraw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, sraw, 0xfffffffff9234567, 0x0000000092345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- diff --git a/isa/rv64ui/srliw.S b/isa/rv64ui/srliw.S index a8b9fd7..471042f 100644 --- a/isa/rv64ui/srliw.S +++ b/isa/rv64ui/srliw.S @@ -35,6 +35,13 @@ RVTEST_CODE_BEGIN TEST_IMM_OP( 15, srliw, 0x0000000000008484, 0x0000000021212121, 14 ); TEST_IMM_OP( 16, srliw, 0x0000000000000000, 0x0000000021212121, 31 ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_IMM_OP( 44, srliw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_IMM_OP( 45, srliw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_IMM_OP( 46, srliw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_IMM_OP( 47, srliw, 0x0000000009234567, 0x0000000092345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- diff --git a/isa/rv64ui/srlw.S b/isa/rv64ui/srlw.S index 24a492a..f0d1dae 100644 --- a/isa/rv64ui/srlw.S +++ b/isa/rv64ui/srlw.S @@ -43,6 +43,13 @@ RVTEST_CODE_BEGIN TEST_RR_OP( 20, srlw, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffee ); TEST_RR_OP( 21, srlw, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + # Verify that shifts ignore top 32 (using true 64-bit values) + + TEST_RR_OP( 44, srlw, 0x0000000012345678, 0xffffffff12345678, 0 ); + TEST_RR_OP( 45, srlw, 0x0000000001234567, 0xffffffff12345678, 4 ); + TEST_RR_OP( 46, srlw, 0xffffffff92345678, 0x0000000092345678, 0 ); + TEST_RR_OP( 47, srlw, 0x0000000009234567, 0x0000000092345678, 4 ); + #------------------------------------------------------------- # Source/Destination tests #------------------------------------------------------------- |