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| author | Neel <neelgala@gmail.com> | 2019-04-20 18:18:39 +0530 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2019-04-20 16:19:22 -0700 |
| commit | a6e2c0dff5cd546cdea704c6122a0250ce096e56 (patch) | |
| tree | 9772abfcd630dd93bc0aa5af0c60774803b91e3f | |
| parent | a6ea2aeca2cae2c2ddac39085217e36c45d1e18b (diff) | |
| download | riscv-tests-a6e2c0dff5cd546cdea704c6122a0250ce096e56.zip riscv-tests-a6e2c0dff5cd546cdea704c6122a0250ce096e56.tar.gz riscv-tests-a6e2c0dff5cd546cdea704c6122a0250ce096e56.tar.bz2 | |
masking no longer required.
| -rw-r--r-- | isa/rv64mi/breakpoint.S | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index c7fbdd4..252a696 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -21,12 +21,6 @@ RVTEST_CODE_BEGIN csrr a1, tselect bne x0, a1, pass - # Make sure there's a breakpoint there. -# csrr a0, tdata1 -# srli a0, a0, __riscv_xlen - 4 -# li a1, 2 -# bne a0, a1, pass - la a2, 1f csrw tdata2, a2 li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_EXECUTE @@ -48,10 +42,8 @@ RVTEST_CODE_BEGIN li TESTNUM, 4 li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD csrw tdata1, a0 - andi a0, a0, 0x7ff # Skip if breakpoint type is unsupported. csrr a1, tdata1 - andi a1, a1, 0x7ff bne a0, a1, 2f la a2, data1 csrw tdata2, a2 @@ -69,10 +61,8 @@ RVTEST_CODE_BEGIN li TESTNUM, 6 li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_STORE csrw tdata1, a0 - andi a0, a0, 0x7ff # Skip if breakpoint type is unsupported. csrr a1, tdata1 - andi a1, a1, 0x7ff bne a0, a1, 2f # Trap handler should skip this instruction. @@ -89,12 +79,6 @@ RVTEST_CODE_BEGIN csrr a1, tselect bne a0, a1, pass - # Make sure there's a breakpoint there. -# csrr a0, tdata1 -# srli a0, a0, __riscv_xlen - 4 -# li a1, 2 -# bne a0, a1, pass - li a0, (2 << (__riscv_xlen - 4)) | MCONTROL_M | MCONTROL_LOAD csrw tdata1, a0 la a3, data2 |