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2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2020-03-16Add a test case rs = rd to jalr.S (#258)Takahiro1-0/+16
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by ↵Cedric Orban1-0/+4
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned
2020-03-06Don't assume reset state of mscratch (#254)Paul Donahue2-13/+13
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset
2020-03-05bump env (#253)Han-Kuan Chen1-12/+12
2020-03-05Bump riscv-test-env (#252)Andrew Waterman1-5/+17
2020-03-05Clean up gdb parsing code. (#247)Tim Newsome1-42/+32
Also fix bug in parsing nan.
2020-03-05Add a simple mechanism to skip tests on targets. (#251)Tim Newsome2-1/+9
2020-03-02enable rv32e compatability by replacing reg x29 with reg x7 (#250)Cedric Orban1-12/+12
2020-02-27bump envAndrew Waterman1-10/+5
2020-02-21scall: make the intention of the test in machine mode more clear (#246)Nils Asmussen1-1/+6
2020-02-20Fix rv64mi-p-csr on systems with FPUsAndrew Waterman1-2/+3
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program.
2020-02-14Add tests for vector register access (#244)Tim Newsome5-34/+137
* WIP * Add vector register smoketest. Also redo the gdb value parsing code to accommodate the more complicated way that vector registers look. * Test vector access a little more thoroughly. * Revert unnecessary changes.
2020-02-11Generate very different values on different harts. (#238)Tim Newsome2-4/+5
This way if you end up reading a value that you suspect might be coming from another hart/register, you can clearly see where it came from.
2020-02-11Run OpenOCD output through spike-dasm. (#239)Tim Newsome1-3/+9
If it's in the path, at least. This way you get human readable assembly in the log instead of hex values.
2020-02-11Look for \bmain\b instead of ' main '. (#237)Tim Newsome1-2/+2
2020-02-08Solves https://github.com/riscv/riscv-tests/issues/241 : Each mhartid has ↵Sho Nakatani1-2/+2
the same size of stack & TLS. (#242)
2020-01-31Added CSR test cases on whether writing 0 to CSR works, as that might get ↵Torbjørn Viem Ness1-0/+2
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236)
2020-01-15Force DMI busy in all tests. (#235)Tim Newsome2-15/+44
This catches more corner cases where this may be a problem.
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome6-13/+231
* WIP * Smoke test virtual address support. Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as large as possible pages to 1:1 map the rest of RAM so those sizes do get minimal coverage as well.
2019-12-28benchmarks: Disassemble .text.init section (#230)Albert Ou1-1/+1
2019-12-24submodule: bump env version (#229)Chih-Min Chao1-5/+10
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome9-7/+27
`make` now takes 31s, `make all` takes 1m53s. The new CheckMisa test ensures that the misa value specified in the configuration is correct.
2019-12-18Tell people where to get software. (#226)Tim Newsome1-3/+9
2019-12-10benchmarks: Simplify TLS initialisation (#224)James Clarke3-19/+5
The symbols used to query the size of .tdata and .tbss need not be thread-local themselves; instead, make them linker script-provided non-thread-local symbols.
2019-12-10Improve parallellism in debug test Makefile (#223)Tim Newsome2-15/+28
* Improve parallellism in debug test Makefile Now each test is an individual make target, so you can get the most out of however many cores you have. On my 12-core system, `make` went from 2m45s to 42s, and `make all` went from `3m25s` to `2m39s`. If you have few cores, this change may actually slow things down a bit, because ExamineTarget is run for every gdbserver.py invocation. * Remove test target.
2019-12-02Use a small binary to set up HiFive Unleashed. (#221)Tim Newsome3-10/+10
This binary comes from https://github.com/timsifive/freedom-u540-c000-bootloader/tree/board_setup2, which will hopefully be accepted upstream.
2019-11-22Move to Python 3. (#218)Tim Newsome4-75/+78
The impetus for this was mostly that after my Ubuntu upgrade, pylint suddenly starting to apply python3 rules, and I suppose it's time to adopt python 3 now that it's been released for more than a decade.
2019-11-04Remove cruft from icache-alias testAndrew Waterman1-35/+0
2019-11-04Add rv64si-p-icache-aliasAndrew Waterman2-0/+177
This test checks that an I$ appears to be physically indexed.
2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome7-3/+191
* Parse inf/nan floats. * Enable mstatus.fs in SimpleF18Test Also accept "unable to fetch" message when FPRs aren't supported. * Add config files for HiFive Unleashed. * Add configs to flash HiFive Unleashed. All tests pass.
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
The latest OpenOCD doesn't need (nor support) this anymore.
2019-09-24Redo the debug README. (#205)Tim Newsome1-26/+19
Hopefully this is enough information that I can simply point people who submit OpenOCD changes to it, and they can run the tests themselves.
2019-09-24Look for binaries in $PATH. (#208)Tim Newsome1-7/+4
Instead of relying on $RISCV. Using $RISCV was common in the early days, but nowadays many tools are simply installed alongside the rest of the system.
2019-09-19Small debug test improvements. (#204)Tim Newsome0-0/+0
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome4-19/+20
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-29Support RV32E. Fixed #198 (#200)Leway Colin3-42/+42
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome5-27/+45
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome2-1/+6
2019-07-01pmp: first set the address, then cfg (#194)Pentin Alexander Sergeevich1-1/+1
2019-06-14Work better with mainline gdb (#192)Tim Newsome2-23/+46
* Parse floats the way mainline gdb prints them. For 64-bit floats, it shows both float and double results. Now more tests pass using mainline gdb. * Disable ANSI when talking to gdb. Helps more tests pass with mainline gdb. * Parse {float=...,double=...} in "info registers" Makes tests work better with mainline gdb.
2019-05-16Cover with/without halt groups. (#191)Tim Newsome5-12/+20
Also work with the new command line options that were renamed in https://github.com/riscv/riscv-isa-sim/pull/299
2019-04-20Merge branch 'neelgala-master'Andrew Waterman1-19/+4
2019-04-20masking no longer required.Neel1-16/+0
2019-04-20removing check for reset value of type in mcontrolNeel1-10/+8
2019-04-20fix for #159 #158Neel1-4/+7
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome7-8/+14
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