Add rv64si-p-icache-alias

This test checks that an I$ appears to be physically indexed.

2 files changed, 177 insertions, 0 deletions

diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag
index c0dbce8..f01a332 100644
--- a/isa/rv64si/Makefrag
+++ b/isa/rv64si/Makefrag
@@ -5,6 +5,7 @@
 rv64si_sc_tests = \
 	csr \
 	dirty \
+	icache-alias \
 	ma_fetch \
 	scall \
 	wfi \
diff --git a/isa/rv64si/icache-alias.S b/isa/rv64si/icache-alias.S
new file mode 100644
index 0000000..15553b1
--- /dev/null
+++ b/isa/rv64si/icache-alias.S
@@ -0,0 +1,176 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# icache-alias.S
+#-----------------------------------------------------------------------------
+#
+# Test that instruction memory appears to be physically addressed, i.e.,
+# that disagreements in the low-order VPN and PPN bits don't cause the
+# wrong instruction to be fetched.  It also tests that changing a page
+# mapping takes effect without executing FENCE.I.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  li TESTNUM, 2
+
+  # Set up intermediate page tables
+
+  la t0, page_table_3
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V
+  sd t0, page_table_2, t1
+
+  la t0, page_table_2
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V
+  sd t0, page_table_1, t1
+
+  # Set up leaf mappings where va[12] != pa[12]
+
+  la t0, code_page_1
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V | PTE_X | PTE_A
+  sd t0, page_table_3 + 8, t1
+
+  la t0, code_page_2
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V | PTE_X | PTE_A
+  sd t0, page_table_3 + 0, t1
+
+  # Turn on VM
+
+  li a0, (SATP_MODE & ~(SATP_MODE<<1)) * SATP_MODE_SV39
+  la a1, page_table_1
+  srl a1, a1, RISCV_PGSHIFT
+  or a1, a1, a0
+  csrw sptbr, a1
+  sfence.vma
+
+  # Enter supervisor mode and make sure correct page is accessed
+
+  la a2, 1f
+  csrwi mepc, 0
+  li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S)
+  csrs mstatus, a1
+  mret
+
+1:
+  li TESTNUM, 2
+  addi a0, a0, -321
+  bnez a0, fail
+
+  li TESTNUM, 3
+  la a2, 1f
+  li t0, RISCV_PGSIZE
+  csrw mepc, t0
+  mret
+
+1:
+  addi a0, a0, -123
+  bnez a0, fail
+
+  li TESTNUM, 4
+  la a2, 1f
+  csrwi mepc, 0
+  mret
+
+  .align 2
+1:
+  addi a0, a0, -321
+  bnez a0, fail
+
+  li TESTNUM, 5
+
+  # Change mapping and try again
+
+  la t0, code_page_1
+  srl t0, t0, RISCV_PGSHIFT - PTE_PPN_SHIFT
+  ori t0, t0, PTE_V | PTE_X | PTE_A
+  sd t0, page_table_3 + 0, t1
+  sfence.vma
+
+  la a2, 1f
+  csrwi mepc, 0
+  mret
+
+  .align 2
+1:
+  addi a0, a0, -123
+  bnez a0, fail
+  
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+  csrr t0, mcause
+  add t0, t0, -CAUSE_STORE_PAGE_FAULT
+  bnez t0, fail
+
+  jr a2
+
+  li t1, 2
+  bne TESTNUM, t1, 1f
+  # Make sure D bit is clear
+  lw t0, page_table_1
+  and t1, t0, PTE_D
+  bnez t1, die
+skip:
+  csrr t0, mepc
+  add t0, t0, 4
+  csrw mepc, t0
+  mret
+
+1:
+  li t1, 3
+  bne TESTNUM, t1, 1f
+  # The implementation doesn't appear to set D bits in HW.
+  # Make sure the D bit really is clear.
+  lw t0, page_table_1
+  and t1, t0, PTE_D
+  bnez t1, die
+  # Set the D bit.
+  or t0, t0, PTE_D
+  sw t0, page_table_1, t1
+  sfence.vma
+  mret
+
+1:
+  li t1, 4
+  bne TESTNUM, t1, 1f
+  j pass
+
+1:
+die:
+  RVTEST_FAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+.align 12
+page_table_1: .dword 0
+.align 12
+page_table_2: .dword 0
+.align 12
+page_table_3: .dword 0
+.align 13
+code_page_1:
+  li a0, 123
+  sw x0, (x0)
+.align 12
+code_page_2:
+  li a0, 321
+  sw x0, (x0)
+
+RVTEST_DATA_END