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author | Tim Newsome <tim@sifive.com> | 2017-09-12 09:36:34 -0700 |
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committer | GitHub <noreply@github.com> | 2017-09-12 09:36:34 -0700 |
commit | 7ab046f286a5356049221946dea36ee755a13346 (patch) | |
tree | 5b8a8f12035b2d29eb08284ab698595b6edce958 /debug/targets/SiFive | |
parent | c2bcbb1a30a1513cc79b9899d41f46870f92a2f3 (diff) | |
parent | a7238f6f683705a92a3216562d91cfc8979c75ed (diff) | |
download | riscv-tests-7ab046f286a5356049221946dea36ee755a13346.zip riscv-tests-7ab046f286a5356049221946dea36ee755a13346.tar.gz riscv-tests-7ab046f286a5356049221946dea36ee755a13346.tar.bz2 |
Merge pull request #69 from riscv/multicore
Proper multicore support for debug tests
Diffstat (limited to 'debug/targets/SiFive')
-rw-r--r-- | debug/targets/SiFive/Freedom/E300.py | 9 | ||||
-rw-r--r-- | debug/targets/SiFive/Freedom/E300Sim.py | 9 | ||||
-rw-r--r-- | debug/targets/SiFive/Freedom/Freedom.lds | 2 | ||||
-rw-r--r-- | debug/targets/SiFive/Freedom/U500.py | 7 | ||||
-rw-r--r-- | debug/targets/SiFive/Freedom/U500Sim.py | 11 | ||||
-rwxr-xr-x | debug/targets/SiFive/HiFive1.lds | 2 | ||||
-rw-r--r-- | debug/targets/SiFive/HiFive1.py | 5 |
7 files changed, 32 insertions, 13 deletions
diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py index 95ddcfd..170de40 100644 --- a/debug/targets/SiFive/Freedom/E300.py +++ b/debug/targets/SiFive/Freedom/E300.py @@ -1,9 +1,12 @@ import targets -class E300(targets.Target): +class E300Hart(targets.Hart): xlen = 32 ram = 0x80000000 - ram_size = 16 * 1024 + ram_size = 256 * 1024 * 1024 instruction_hardware_breakpoint_count = 2 - openocd_config_path = "Freedom.cfg" link_script_path = "Freedom.lds" + +class E300(targets.Target): + openocd_config_path = "Freedom.cfg" + harts = [E300Hart()] diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py index 91be2e8..f9428d0 100644 --- a/debug/targets/SiFive/Freedom/E300Sim.py +++ b/debug/targets/SiFive/Freedom/E300Sim.py @@ -1,14 +1,17 @@ import targets import testlib -class E300Sim(targets.Target): +class E300Hart(targets.Hart): xlen = 32 - timeout_sec = 6000 ram = 0x80000000 ram_size = 256 * 1024 * 1024 instruction_hardware_breakpoint_count = 2 - openocd_config_path = "Freedom.cfg" link_script_path = "Freedom.lds" +class E300Sim(targets.Target): + timeout_sec = 6000 + openocd_config_path = "Freedom.cfg" + harts = [E300Hart()] + def create(self): return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) diff --git a/debug/targets/SiFive/Freedom/Freedom.lds b/debug/targets/SiFive/Freedom/Freedom.lds index 1e0645a..9354d3f 100644 --- a/debug/targets/SiFive/Freedom/Freedom.lds +++ b/debug/targets/SiFive/Freedom/Freedom.lds @@ -20,11 +20,13 @@ SECTIONS } /* bss segment */ + __bss_start = .; .sbss : { *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } .bss : { *(.bss) } + __bss_end = .; __malloc_start = .; . = . + 512; diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py index c22aa4c..6da3ac5 100644 --- a/debug/targets/SiFive/Freedom/U500.py +++ b/debug/targets/SiFive/Freedom/U500.py @@ -1,9 +1,12 @@ import targets -class U500(targets.Target): +class U500Hart(targets.Hart): xlen = 64 ram = 0x80000000 ram_size = 16 * 1024 instruction_hardware_breakpoint_count = 2 - openocd_config_path = "Freedom.cfg" link_script_path = "Freedom.lds" + +class U500(targets.Target): + openocd_config_path = "Freedom.cfg" + harts = [U500Hart()] diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py index 62bc827..065ab08 100644 --- a/debug/targets/SiFive/Freedom/U500Sim.py +++ b/debug/targets/SiFive/Freedom/U500Sim.py @@ -1,14 +1,17 @@ import targets import testlib -class U500Sim(targets.Target): +class U500Hart(targets.Hart): xlen = 64 - timeout_sec = 6000 ram = 0x80000000 ram_size = 256 * 1024 * 1024 instruction_hardware_breakpoint_count = 2 - openocd_config_path = "Freedom.cfg" link_script_path = "Freedom.lds" - def create(self): +class U500Sim(targets.Target): + timeout_sec = 6000 + openocd_config_path = "Freedom.cfg" + harts = [U500Hart()] + + def target(self): return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False) diff --git a/debug/targets/SiFive/HiFive1.lds b/debug/targets/SiFive/HiFive1.lds index 1e0645a..9354d3f 100755 --- a/debug/targets/SiFive/HiFive1.lds +++ b/debug/targets/SiFive/HiFive1.lds @@ -20,11 +20,13 @@ SECTIONS } /* bss segment */ + __bss_start = .; .sbss : { *(.sbss .sbss.* .gnu.linkonce.sb.*) *(.scommon) } .bss : { *(.bss) } + __bss_end = .; __malloc_start = .; . = . + 512; diff --git a/debug/targets/SiFive/HiFive1.py b/debug/targets/SiFive/HiFive1.py index 813829e..3cb508c 100644 --- a/debug/targets/SiFive/HiFive1.py +++ b/debug/targets/SiFive/HiFive1.py @@ -1,8 +1,11 @@ import targets -class HiFive1(targets.Target): +class HiFive1Hart(targets.Hart): xlen = 32 ram = 0x80000000 ram_size = 16 * 1024 instruction_hardware_breakpoint_count = 2 misa = 0x40001105 + +class HiFive1(targets.Target): + harts = [HiFive1Hart()] |