U500.py\Freedom\SiFive\targets\debug - riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

index : riscv-tests.git

Unnamed repository; edit this file 'description' to name the repository.

root

about summary refs log tree commit diff

path: root/debug/targets/SiFive/Freedom/U500.py

blob: c22aa4c6907fd3b280550e812f558dc05b627812 (plain)

import targets

class U500(targets.Target):
    xlen = 64
    ram = 0x80000000
    ram_size = 16 * 1024
    instruction_hardware_breakpoint_count = 2
    openocd_config_path = "Freedom.cfg"
    link_script_path = "Freedom.lds"