Merge pull request #69 from riscv/multicore

Proper multicore support for debug tests

15 files changed, 75 insertions, 38 deletions

diff --git a/debug/targets/RISC-V/spike32.cfg b/debug/targets/RISC-V/spike.cfg
index 2742335..9b1841c 100644
--- a/debug/targets/RISC-V/spike32.cfg
+++ b/debug/targets/RISC-V/spike.cfg
@@ -8,12 +8,9 @@ set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable
 
 init
 reset halt
-
-echo "Ready for Remote Connections"
diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
new file mode 100644
index 0000000..6cf558d
--- /dev/null
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+import spike32  # pylint: disable=import-error
+
+class spike32_2(targets.Target):
+    harts = [spike32.spike32_hart(), spike32.spike32_hart()]
+    openocd_config_path = "spike.cfg"
+    timeout_sec = 30
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike32.lds b/debug/targets/RISC-V/spike32.lds
index 01d0e3d..84216db 100755
--- a/debug/targets/RISC-V/spike32.lds
+++ b/debug/targets/RISC-V/spike32.lds
@@ -22,11 +22,13 @@ SECTIONS
   }
 
   /* bss segment */
+  __bss_start = .;
   .sbss : {
     *(.sbss .sbss.* .gnu.linkonce.sb.*)
     *(.scommon)
   }
   .bss : { *(.bss) }
+  __bss_end = .;
 
   __malloc_start = .;
   . = . + 512;
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
index 3bf8b47..665d7e9 100644
--- a/debug/targets/RISC-V/spike32.py
+++ b/debug/targets/RISC-V/spike32.py
@@ -1,12 +1,18 @@
 import targets
 import testlib
 
-class spike32(targets.Target):
+class spike32_hart(targets.Hart):
     xlen = 32
     ram = 0x10000000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
+    link_script_path = "spike32.lds"
+
+class spike32(targets.Target):
+    harts = [spike32_hart()]
+    openocd_config_path = "spike.cfg"
+    timeout_sec = 30
 
     def create(self):
         return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64-2.py b/debug/targets/RISC-V/spike64-2.py
new file mode 100644
index 0000000..c6321dc
--- /dev/null
+++ b/debug/targets/RISC-V/spike64-2.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+import spike64  # pylint: disable=import-error
+
+class spike64_2(targets.Target):
+    harts = [spike64.spike64_hart(), spike64.spike64_hart()]
+    openocd_config_path = "spike.cfg"
+    timeout_sec = 30
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64.cfg b/debug/targets/RISC-V/spike64.cfg
deleted file mode 100644
index 2742335..0000000
--- a/debug/targets/RISC-V/spike64.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-adapter_khz     10000
-
-interface remote_bitbang
-remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
-remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
-
-set _TARGETNAME $_CHIPNAME.cpu
-#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-gdb_report_data_abort enable
-
-init
-reset halt
-
-echo "Ready for Remote Connections"
diff --git a/debug/targets/RISC-V/spike64.lds b/debug/targets/RISC-V/spike64.lds
index dc7cb63..2e7d65d 100755
--- a/debug/targets/RISC-V/spike64.lds
+++ b/debug/targets/RISC-V/spike64.lds
@@ -20,11 +20,13 @@ SECTIONS
   }
 
   /* bss segment */
+  __bss_start = .;
   .sbss : {
     *(.sbss .sbss.* .gnu.linkonce.sb.*)
     *(.scommon)
   }
   .bss : { *(.bss) }
+  __bss_end = .;
 
   __malloc_start = .;
   . = . + 512;
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index c705857..6e3da89 100644
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -1,12 +1,18 @@
 import targets
 import testlib
 
-class spike64(targets.Target):
+class spike64_hart(targets.Hart):
     xlen = 64
     ram = 0x1212340000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
+    link_script_path = "spike64.lds"
+
+class spike64(targets.Target):
+    harts = [spike64_hart()]
+    openocd_config_path = "spike.cfg"
+    timeout_sec = 30
 
     def create(self):
         return testlib.Spike(self)
diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py
index 95ddcfd..170de40 100644
--- a/debug/targets/SiFive/Freedom/E300.py
+++ b/debug/targets/SiFive/Freedom/E300.py
@@ -1,9 +1,12 @@
 import targets
 
-class E300(targets.Target):
+class E300Hart(targets.Hart):
     xlen = 32
     ram = 0x80000000
-    ram_size = 16 * 1024
+    ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
+
+class E300(targets.Target):
+    openocd_config_path = "Freedom.cfg"
+    harts = [E300Hart()]
diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py
index 91be2e8..f9428d0 100644
--- a/debug/targets/SiFive/Freedom/E300Sim.py
+++ b/debug/targets/SiFive/Freedom/E300Sim.py
@@ -1,14 +1,17 @@
 import targets
 import testlib
 
-class E300Sim(targets.Target):
+class E300Hart(targets.Hart):
     xlen = 32
-    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
 
+class E300Sim(targets.Target):
+    timeout_sec = 6000
+    openocd_config_path = "Freedom.cfg"
+    harts = [E300Hart()]
+
     def create(self):
         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/targets/SiFive/Freedom/Freedom.lds b/debug/targets/SiFive/Freedom/Freedom.lds
index 1e0645a..9354d3f 100644
--- a/debug/targets/SiFive/Freedom/Freedom.lds
+++ b/debug/targets/SiFive/Freedom/Freedom.lds
@@ -20,11 +20,13 @@ SECTIONS
   }
 
   /* bss segment */
+  __bss_start = .;
   .sbss : {
     *(.sbss .sbss.* .gnu.linkonce.sb.*)
     *(.scommon)
   }
   .bss : { *(.bss) }
+  __bss_end = .;
 
   __malloc_start = .;
   . = . + 512;
diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py
index c22aa4c..6da3ac5 100644
--- a/debug/targets/SiFive/Freedom/U500.py
+++ b/debug/targets/SiFive/Freedom/U500.py
@@ -1,9 +1,12 @@
 import targets
 
-class U500(targets.Target):
+class U500Hart(targets.Hart):
     xlen = 64
     ram = 0x80000000
     ram_size = 16 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
+
+class U500(targets.Target):
+    openocd_config_path = "Freedom.cfg"
+    harts = [U500Hart()]
diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
index 62bc827..065ab08 100644
--- a/debug/targets/SiFive/Freedom/U500Sim.py
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -1,14 +1,17 @@
 import targets
 import testlib
 
-class U500Sim(targets.Target):
+class U500Hart(targets.Hart):
     xlen = 64
-    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
-    openocd_config_path = "Freedom.cfg"
     link_script_path = "Freedom.lds"
 
-    def create(self):
+class U500Sim(targets.Target):
+    timeout_sec = 6000
+    openocd_config_path = "Freedom.cfg"
+    harts = [U500Hart()]
+
+    def target(self):
         return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/targets/SiFive/HiFive1.lds b/debug/targets/SiFive/HiFive1.lds
index 1e0645a..9354d3f 100755
--- a/debug/targets/SiFive/HiFive1.lds
+++ b/debug/targets/SiFive/HiFive1.lds
@@ -20,11 +20,13 @@ SECTIONS
   }
 
   /* bss segment */
+  __bss_start = .;
   .sbss : {
     *(.sbss .sbss.* .gnu.linkonce.sb.*)
     *(.scommon)
   }
   .bss : { *(.bss) }
+  __bss_end = .;
 
   __malloc_start = .;
   . = . + 512;
diff --git a/debug/targets/SiFive/HiFive1.py b/debug/targets/SiFive/HiFive1.py
index 813829e..3cb508c 100644
--- a/debug/targets/SiFive/HiFive1.py
+++ b/debug/targets/SiFive/HiFive1.py
@@ -1,8 +1,11 @@
 import targets
 
-class HiFive1(targets.Target):
+class HiFive1Hart(targets.Hart):
     xlen = 32
     ram = 0x80000000
     ram_size = 16 * 1024
     instruction_hardware_breakpoint_count = 2
     misa = 0x40001105
+
+class HiFive1(targets.Target):
+    harts = [HiFive1Hart()]