| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2015-09-08 | Refer to LICENSE in some newer source files | Andrew Waterman | 1 | -0/+2 |
| 2015-03-12 | Update to new privileged spec | Andrew Waterman | 1 | -1/+0 |
| 2013-11-05 | correctly trap when SR_EA is disabled | Yunsup Lee | 1 | -0/+1 |
| 2013-10-18 | refactor disassembler, and add hwacha disassembler | Yunsup Lee | 1 | -0/+6 |
| 2013-10-17 | fix custom-1 rocc encoding | Yunsup Lee | 1 | -1/+1 |
| 2013-10-16 | revamp hwacha; now runs in physical mode | Yunsup Lee | 1 | -6/+0 |
| 2013-10-15 | Fix bug where xs2 was not being properly respected. | Stephen Twigg | 1 | -1/+1 |
| 2013-09-27 | Use WRITE_RD/WRITE_FRD macros to write registers | Andrew Waterman | 1 | -1/+1 |
| 2013-08-13 | Implement RoCC and add a dummy RoCC | Andrew Waterman | 1 | -0/+44 |
 |
index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
| aboutsummaryrefslogtreecommitdiff |