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author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-13 00:51:07 -0700 |
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committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-08-13 00:51:07 -0700 |
commit | bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417 (patch) | |
tree | 63bcac40261140f5628d1e12182d658005eae300 /riscv/rocc.cc | |
parent | 04c2d491c4bbb424a59273d4ebee62ddfe3379f9 (diff) | |
download | riscv-isa-sim-bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417.zip riscv-isa-sim-bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417.tar.gz riscv-isa-sim-bbb0f2179c858c77918ef37dbfcd7bb5f3fd0417.tar.bz2 |
Implement RoCC and add a dummy RoCC
Enable it with --extension=dummy
Diffstat (limited to 'riscv/rocc.cc')
-rw-r--r-- | riscv/rocc.cc | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/riscv/rocc.cc b/riscv/rocc.cc new file mode 100644 index 0000000..3e8596f --- /dev/null +++ b/riscv/rocc.cc @@ -0,0 +1,44 @@ +#include "rocc.h" +#include "trap.h" +#include <cstdlib> + +union rocc_insn_union_t +{ + rocc_insn_t r; + insn_t i; +}; + +#define customX(n) \ + static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ + { \ + rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \ + rocc_insn_union_t u; \ + u.i = insn; \ + reg_t xs1 = u.r.xs1 ? RS1 : -1; \ + reg_t xs2 = u.r.xs1 ? RS2 : -1; \ + reg_t xd = rocc->custom##n(u.r, xs1, xs2); \ + if (u.r.xd) \ + RD = xd; \ + return pc+4; \ + } \ + \ + reg_t rocc_t::custom##n(rocc_insn_t insn, reg_t xs1, reg_t xs2) \ + { \ + illegal_instruction(); \ + return 0; \ + } + +customX(0) +customX(1) +customX(2) +customX(3) + +std::vector<insn_desc_t> rocc_t::get_instructions() +{ + std::vector<insn_desc_t> insns; + insns.push_back((insn_desc_t){0x0b, 0x7f, &::illegal_instruction, c0}); + insns.push_back((insn_desc_t){0x0f, 0x7f, &::illegal_instruction, c1}); + insns.push_back((insn_desc_t){0x5b, 0x7f, &::illegal_instruction, c2}); + insns.push_back((insn_desc_t){0x7b, 0x7f, &::illegal_instruction, c3}); + return insns; +} |