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author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 21:01:34 -0800 |
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committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-05 21:01:34 -0800 |
commit | d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be (patch) | |
tree | d4a1fd090ff86f43eab75b3eb6e1195ab52c59e0 /riscv/rocc.cc | |
parent | 692ba09ef40c0cec66304678808db01e23e7b2ec (diff) | |
download | riscv-isa-sim-d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be.zip riscv-isa-sim-d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be.tar.gz riscv-isa-sim-d0a84535eb6f1fcd0edd8928ace16dcdbe0c48be.tar.bz2 |
correctly trap when SR_EA is disabled
Diffstat (limited to 'riscv/rocc.cc')
-rw-r--r-- | riscv/rocc.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/rocc.cc b/riscv/rocc.cc index 7988c01..e51aee5 100644 --- a/riscv/rocc.cc +++ b/riscv/rocc.cc @@ -5,6 +5,7 @@ #define customX(n) \ static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \ { \ + require_accelerator; \ rocc_t* rocc = static_cast<rocc_t*>(p->get_extension()); \ rocc_insn_union_t u; \ u.i = insn; \ |