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riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speed2
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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Author
Files
Lines
2013-09-27
Added commit logging (--enable-commitlog). Also fixed disasm bug.
Christopher Celio
1
-0
/
+5
2013-07-26
Remove more vector stuff
Andrew Waterman
1
-10
/
+0
2013-01-25
change htif to link against libfesvr
Andrew Waterman
1
-2
/
+13
2011-11-11
Remove dependence on binutils
Your Name
1
-16
/
+0
2011-11-11
Use new compiler toolchain's disassembler
Andrew Waterman
1
-1
/
+1
2011-07-08
bugfix to riscv.ac
Rimas Avizienis
1
-2
/
+2
2011-07-08
fixes to make disassembly work under macos (with macports binutils installed)
Rimas Avizienis
1
-1
/
+6
2011-06-19
temporary undoing of renaming
Andrew Waterman
1
-0
/
+32
2011-06-12
[sim] renamed to riscv-isa-run
Andrew Waterman
1
-37
/
+0
2011-06-11
[xcc] fix configure scripts
Andrew Waterman
1
-3
/
+3
2011-04-15
[sim] added icache simulator (disabled by default)
Andrew Waterman
1
-0
/
+5
2011-04-09
[sim] add disable option for vector
Yunsup Lee
1
-0
/
+5
2011-04-09
[sim,pk] reorganized status register
Andrew Waterman
1
-0
/
+5
2010-10-15
[pk, sim] added FPU emulation support to proxy kernel
Andrew Waterman
1
-0
/
+10
2010-07-18
Reorganized directory structure
Andrew Waterman
1
-0
/
+12