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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-09 20:18:04 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-04-09 20:18:36 -0700 |
| commit | 4b534147c0c49f9ea57f4c686af7c6508d114a99 (patch) | |
| tree | 2c905ba04c04f1f63a872d7e0b269c97197e7ebf /riscv/riscv.ac | |
| parent | 7198e5091fa9d2606a993cae45f9c90e170f3103 (diff) | |
| download | riscv-isa-sim-4b534147c0c49f9ea57f4c686af7c6508d114a99.zip riscv-isa-sim-4b534147c0c49f9ea57f4c686af7c6508d114a99.tar.gz riscv-isa-sim-4b534147c0c49f9ea57f4c686af7c6508d114a99.tar.bz2 | |
[sim] add disable option for vector
Diffstat (limited to 'riscv/riscv.ac')
| -rw-r--r-- | riscv/riscv.ac | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 9bb4f2f..36c701a 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -13,6 +13,11 @@ AS_IF([test "x$enable_rvc" != "xno"], [ AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) ]) +AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor])) +AS_IF([test "x$enable_vec" != "xno"], [ + AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) +]) + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"]) |