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AgeCommit message (Expand)AuthorFilesLines
2013-10-15Propogate the reset call to the extensions as well. Add reset function to ext...Stephen Twigg1-1/+2
2013-09-27Added commit logging (--enable-commitlog). Also fixed disasm bug.Christopher Celio1-0/+16
2013-09-23fixes compile bug for not being able to find std::logic_errorScott Beamer1-0/+1
2013-09-11Implement zany immediatesAndrew Waterman1-6/+6
2013-08-18Renumber PCRsAndrew Waterman1-4/+4
2013-08-13Implement RoCC and add a dummy RoCCAndrew Waterman1-27/+29
2013-08-11Instructions are no longer member functionsAndrew Waterman1-83/+98
2013-07-26New supervisor modeAndrew Waterman1-6/+9
2013-07-26Remove more vector stuffAndrew Waterman1-49/+2
2013-07-26Rip out Hwacha for nowAndrew Waterman1-8/+0
2013-07-26Rip out RVC for nowAndrew Waterman1-1/+1
2013-07-26Generate instruction decoder dynamicallyAndrew Waterman1-3/+48
2013-07-22Add xspike programAndrew Waterman1-6/+6
2013-04-25use inttypes macros to print uint64_tAndrew Waterman1-7/+8
2013-04-24fixes to correctly simulate the vector unitYunsup Lee1-0/+2
2013-03-29add load-reserved/store-conditional instructionsAndrew Waterman1-3/+0
2013-03-29ignore writes to SR IP fieldAndrew Waterman1-2/+3
2013-03-25add BSD licenseAndrew Waterman1-0/+2
2013-03-25truncate effective addresses in rv32Andrew Waterman1-2/+1
2013-03-25expose pending interrupts in status registerAndrew Waterman1-7/+14
2013-02-13clean up fetch-execute loop a bitAndrew Waterman1-12/+4
2012-11-13fix vector code simulation problem, turn on SR_U64Yunsup Lee1-1/+1
2012-08-30new tohost/fromhost semanticsAndrew Waterman1-1/+2
2012-08-01new tohost/fromhost semanticsAndrew Waterman1-2/+0
2012-07-22correct HTIF reset behaviorAndrew Waterman1-17/+12
2012-05-09per-core tohost/fromhost registersAndrew Waterman1-7/+22
2012-03-24new supervisor modeAndrew Waterman1-34/+114
2012-03-19abstract regfile behind objectAndrew Waterman1-2/+2
2011-12-10fix utidx assign bug, make ut code execute fasterYunsup Lee1-1/+2
2011-11-11Remove dependence on binutilsYour Name1-23/+5
2011-11-11Use new compiler toolchain's disassemblerAndrew Waterman1-3/+5
2011-11-11Changed supervisor modeAndrew Waterman1-9/+14
2011-06-19temporary undoing of renamingAndrew Waterman1-0/+240
2011-06-12[sim] renamed to riscv-isa-runAndrew Waterman1-273/+0
2011-06-12[xcc] minor performance tweaksAndrew Waterman1-4/+10
2011-06-11[xcc] fixed simulator build timeAndrew Waterman1-52/+0
2011-06-11[xcc] cleaned up mmu codeAndrew Waterman1-3/+3
2011-06-10[sim, opcodes] made sim more decoupled from opcodesAndrew Waterman1-3/+53
2011-05-31[sim] minor sim cleanupAndrew Waterman1-2/+2
2011-05-29[sim,opcodes] improved sim build and run performanceAndrew Waterman1-27/+48
2011-05-28[fesvr,xcc,sim] fixed multicore sim for akarosAndrew Waterman1-30/+48
2011-05-23[sim,xcc] add rdcycle/rdtime/rdinstretAndrew Waterman1-2/+2
2011-05-19[sim] change default hwvlYunsup Lee1-3/+3
2011-05-19[sim] vlen calc reflects the hardwareYunsup Lee1-9/+6
2011-05-16[sim,pk] cleanups & initial virtual memory supportAndrew Waterman1-0/+1
2011-05-13[sim] initial support for virtual memoryAndrew Waterman1-0/+3
2011-04-30[sim] hacked in a dcache simulatorAndrew Waterman1-5/+29
2011-04-15[sim] added icache simulator (disabled by default)Andrew Waterman1-2/+18
2011-04-11[xcc,sim,opcodes] more rvc instructions and bug fixesAndrew Waterman1-1/+2
2011-04-09[sim] add disable option for vectorYunsup Lee1-0/+3
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