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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-22 14:48:54 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-22 14:48:54 -0700 |
| commit | a68c33c2a4c6278e7cce58f8a668cb24f636d024 (patch) | |
| tree | e908f1a3790c0e1184083789d633da3402d581af /riscv/processor.cc | |
| parent | 97a9245bdd3de9b9a58a684a4e8b2fe7772a0e2a (diff) | |
| download | riscv-isa-sim-a68c33c2a4c6278e7cce58f8a668cb24f636d024.zip riscv-isa-sim-a68c33c2a4c6278e7cce58f8a668cb24f636d024.tar.gz riscv-isa-sim-a68c33c2a4c6278e7cce58f8a668cb24f636d024.tar.bz2 | |
Add xspike program
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 74a98a8..843279b 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -177,11 +177,11 @@ void processor_t::take_trap(reg_t t, bool noisy) if(noisy) { if ((sreg_t)t < 0) - printf("core %3d: interrupt %d, epc 0x%016" PRIx64 "\n", - id, uint8_t(t), pc); + fprintf(stderr, "core %3d: interrupt %d, epc 0x%016" PRIx64 "\n", + id, uint8_t(t), pc); else - printf("core %3d: trap %s, epc 0x%016" PRIx64 "\n", - id, trap_name(trap_t(t)), pc); + fprintf(stderr, "core %3d: trap %s, epc 0x%016" PRIx64 "\n", + id, trap_name(trap_t(t)), pc); } // switch to supervisor, set previous supervisor bit, disable traps @@ -202,8 +202,8 @@ void processor_t::disasm(insn_t insn, reg_t pc) { // the disassembler is stateless, so we share it static disassembler disasm; - printf("core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n", - id, pc, insn.bits, disasm.disassemble(insn).c_str()); + fprintf(stderr, "core %3d: 0x%016" PRIx64 " (0x%08" PRIx32 ") %s\n", + id, pc, insn.bits, disasm.disassemble(insn).c_str()); } void processor_t::set_pcr(int which, reg_t val) |