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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 04:15:57 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2013-07-26 04:15:57 -0700 |
| commit | 5a97139eeecac32b8127393be7fcdb23a8e98ff6 (patch) | |
| tree | 610f3be4d6d45ddc02f7df9f6cc0545094b0f79f /riscv/processor.cc | |
| parent | 0de1489e8ab4a527fbcb1440a8fd5b2d4c8c9260 (diff) | |
| download | riscv-isa-sim-5a97139eeecac32b8127393be7fcdb23a8e98ff6.zip riscv-isa-sim-5a97139eeecac32b8127393be7fcdb23a8e98ff6.tar.gz riscv-isa-sim-5a97139eeecac32b8127393be7fcdb23a8e98ff6.tar.bz2 | |
Rip out RVC for now
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 5d82937..3bd4a19 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -132,7 +132,7 @@ void processor_t::step(size_t n, bool noisy) // execute_insn fetches and executes one instruction #define execute_insn(noisy) \ do { \ - mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc, sr & SR_EC); \ + mmu_t::insn_fetch_t fetch = _mmu.load_insn(npc); \ if(noisy) disasm(fetch.insn, npc); \ npc = fetch.func(this, fetch.insn, npc); \ pc = npc; \ |