| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-05-28 | rvv: add new explicit eew load/store instructions | Chih-Min Chao | 1 | -3/+0 |
| 2020-04-24 | rvv: leave only SEW-bit segment load | Chih-Min Chao | 1 | -2/+2 |
| 2019-06-18 | rvv: add load/store instructions | Chih-Min Chao | 1 | -0/+3 |
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index : riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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