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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-13 01:48:26 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-24 00:24:58 -0700 |
| commit | 81686eae2ee2b7ecdce100c6a424db8e1349ec09 (patch) | |
| tree | c4ad8e5e4fc582498c744ae66d1607ec54859f3e /riscv/insns/vlswu_v.h | |
| parent | 7b3d88f5de4e47c989e64d49498233ecda928b09 (diff) | |
| download | riscv-isa-sim-81686eae2ee2b7ecdce100c6a424db8e1349ec09.zip riscv-isa-sim-81686eae2ee2b7ecdce100c6a424db8e1349ec09.tar.gz riscv-isa-sim-81686eae2ee2b7ecdce100c6a424db8e1349ec09.tar.bz2 | |
rvv: leave only SEW-bit segment load
new features in spec 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/insns/vlswu_v.h')
| -rw-r--r-- | riscv/insns/vlswu_v.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/vlswu_v.h b/riscv/insns/vlswu_v.h index 865af22..f509076 100644 --- a/riscv/insns/vlswu_v.h +++ b/riscv/insns/vlswu_v.h @@ -1,3 +1,3 @@ -// vlsw.v and vlsseg[2-8]w.v +// vlsw.v require(P.VU.vsew >= e32); -VI_LD(i * RS2, fn, uint32, 4); +VI_LD(i * RS2, fn, uint32, 4, false); |