diff options
| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:34:26 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-10-17 19:34:26 -0700 |
| commit | 0f140bcde46a940f76d3e06857d3f572ab6966c4 (patch) | |
| tree | b6f8bb4215691c4a730d323d62ec82282f90e4ff /riscv | |
| parent | 289e2118cb35c023c04085e731952edb70fc18a9 (diff) | |
| download | riscv-isa-sim-0f140bcde46a940f76d3e06857d3f572ab6966c4.zip riscv-isa-sim-0f140bcde46a940f76d3e06857d3f572ab6966c4.tar.gz riscv-isa-sim-0f140bcde46a940f76d3e06857d3f572ab6966c4.tar.bz2 | |
add hwacha exception support
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/pcr.h | 11 | ||||
| -rw-r--r-- | riscv/trap.h | 4 |
2 files changed, 1 insertions, 14 deletions
diff --git a/riscv/pcr.h b/riscv/pcr.h index 8780cdd..75a349f 100644 --- a/riscv/pcr.h +++ b/riscv/pcr.h @@ -59,17 +59,6 @@ #define CAUSE_MISALIGNED_STORE 9 #define CAUSE_FAULT_LOAD 10 #define CAUSE_FAULT_STORE 11 -#define CAUSE_VECTOR_DISABLED 12 -#define CAUSE_VECTOR_BANK 13 - -#define CAUSE_VECTOR_MISALIGNED_FETCH 24 -#define CAUSE_VECTOR_FAULT_FETCH 25 -#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26 -#define CAUSE_VECTOR_ILLEGAL_COMMAND 27 -#define CAUSE_VECTOR_MISALIGNED_LOAD 28 -#define CAUSE_VECTOR_MISALIGNED_STORE 29 -#define CAUSE_VECTOR_FAULT_LOAD 30 -#define CAUSE_VECTOR_FAULT_STORE 31 // page table entry (PTE) fields #define PTE_V 0x001 // Entry is a page Table descriptor diff --git a/riscv/trap.h b/riscv/trap.h index a7a823b..9a1a2f9 100644 --- a/riscv/trap.h +++ b/riscv/trap.h @@ -25,6 +25,7 @@ class mem_trap_t : public trap_t mem_trap_t(reg_t which, reg_t badvaddr) : trap_t(which), badvaddr(badvaddr) {} void side_effects(state_t* state); + reg_t get_badvaddr() { return badvaddr; } private: reg_t badvaddr; }; @@ -53,8 +54,5 @@ DECLARE_MEM_TRAP(8, load_address_misaligned) DECLARE_MEM_TRAP(9, store_address_misaligned) DECLARE_MEM_TRAP(10, load_access_fault) DECLARE_MEM_TRAP(11, store_access_fault) -DECLARE_TRAP(12, vector_disabled) -DECLARE_TRAP(13, vector_bank) -DECLARE_TRAP(14, vector_illegal_instruction) #endif |