From 4b534147c0c49f9ea57f4c686af7c6508d114a99 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 9 Apr 2011 20:18:04 -0700 Subject: [sim] add disable option for vector --- riscv/riscv.ac | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'riscv/riscv.ac') diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 9bb4f2f..36c701a 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -13,6 +13,11 @@ AS_IF([test "x$enable_rvc" != "xno"], [ AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) ]) +AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor])) +AS_IF([test "x$enable_vec" != "xno"], [ + AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) +]) + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"]) -- cgit v1.1