diff options
| -rw-r--r-- | config.h.in | 3 | ||||
| -rwxr-xr-x | configure | 15 | ||||
| -rw-r--r-- | riscv/processor.cc | 3 | ||||
| -rw-r--r-- | riscv/riscv.ac | 5 |
4 files changed, 26 insertions, 0 deletions
diff --git a/config.h.in b/config.h.in index fb0f56f..e592810 100644 --- a/config.h.in +++ b/config.h.in @@ -30,6 +30,9 @@ /* Define if instruction compression is supported */ #undef RISCV_ENABLE_RVC +/* Define if vector processor is supported */ +#undef RISCV_ENABLE_VEC + /* Define if libopcodes exists */ #undef RISCV_HAVE_LIBOPCODES @@ -638,6 +638,7 @@ enable_optional_subprojects enable_fpu enable_64bit enable_rvc +enable_vec ' ac_precious_vars='build_alias host_alias @@ -1273,6 +1274,7 @@ Optional Features: --disable-fpu Disable floating-point --disable-64bit Disable 64-bit mode --disable-rvc Disable instruction compression + --disable-vec Disable vector processor Some influential environment variables: CC C compiler command @@ -4060,6 +4062,19 @@ $as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h fi +# Check whether --enable-vec was given. +if test "${enable_vec+set}" = set; then : + enableval=$enable_vec; +fi + +if test "x$enable_vec" != "xno"; then : + + +$as_echo "#define RISCV_ENABLE_VEC /**/" >>confdefs.h + + +fi + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a as_ac_File=`$as_echo "ac_cv_file_$libopc" | $as_tr_sh` { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $libopc" >&5 diff --git a/riscv/processor.cc b/riscv/processor.cc index 3185908..f9c8bea 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -77,6 +77,9 @@ void processor_t::set_sr(uint32_t val) #ifndef RISCV_ENABLE_RVC sr &= ~SR_EC; #endif +#ifndef RISCV_ENABLE_VEC + sr &= ~SR_EV; +#endif xprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32; } diff --git a/riscv/riscv.ac b/riscv/riscv.ac index 9bb4f2f..36c701a 100644 --- a/riscv/riscv.ac +++ b/riscv/riscv.ac @@ -13,6 +13,11 @@ AS_IF([test "x$enable_rvc" != "xno"], [ AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported]) ]) +AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor])) +AS_IF([test "x$enable_vec" != "xno"], [ + AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported]) +]) + libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"]) |