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| author | Andrew Waterman <andrew@sifive.com> | 2026-02-13 15:30:01 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2026-02-13 15:47:33 -0800 |
| commit | a1cf82541b565c88f87a270f191aaaac5f03978f (patch) | |
| tree | 63810401b76bfec4dc5863527d58c65b55c0918b /riscv/processor.cc | |
| parent | eb6586e3dea4a622bcdd4d518b25f8202b90eb40 (diff) | |
| download | riscv-isa-sim-fetch.zip riscv-isa-sim-fetch.tar.gz riscv-isa-sim-fetch.tar.bz2 | |
Speed up I$ refillfetch
Leverage the vastly common case that instructions are only 2 or 4 bytes,
hit in the TLB, and do not span a page boundary.
Diffstat (limited to 'riscv/processor.cc')
| -rw-r--r-- | riscv/processor.cc | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 80a47d9..5c4bfe2 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -653,17 +653,6 @@ reg_t processor_t::throw_instruction_address_misaligned(reg_t pc) throw trap_instruction_address_misaligned(state.v, pc, 0, 0); } -insn_func_t processor_t::decode_insn(insn_t insn) -{ - const auto& pool = opcode_map[insn.bits() % std::size(opcode_map)]; - - for (auto p = pool.begin(); ; ++p) { - if ((insn.bits() & p->mask) == p->match) { - return p->func; - } - } -} - void processor_t::register_insn(insn_desc_t desc, std::vector<insn_desc_t>& pool) { assert(desc.fast_rv32i && desc.fast_rv64i && desc.fast_rv32e && desc.fast_rv64e && desc.logged_rv32i && desc.logged_rv64i && desc.logged_rv32e && desc.logged_rv64e); |
