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| author | Daniel Lustig <dlustig@nvidia.com> | 2021-08-06 20:19:02 -0400 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-06 17:19:02 -0700 |
| commit | a477155179bb2b7bcda78a755c46a5490a336484 (patch) | |
| tree | c5feb39fff207d84a3fee124c3a335d09e5ee12a /riscv/mmu.cc | |
| parent | 866b31ff9b05192965053a3b802967465febdeee (diff) | |
| download | riscv-isa-sim-a477155179bb2b7bcda78a755c46a5490a336484.zip riscv-isa-sim-a477155179bb2b7bcda78a755c46a5490a336484.tar.gz riscv-isa-sim-a477155179bb2b7bcda78a755c46a5490a336484.tar.bz2 | |
Non-leaf PTEs should not have N or PBMT bits set (#764)
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 5b0c31b..e57e81c 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -332,7 +332,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty if (pte & PTE_RSVD) { break; } else if (PTE_TABLE(pte)) { // next level of page table - if (pte & (PTE_D | PTE_A | PTE_U)) + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) break; base = ppn << PGSHIFT; } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) { @@ -417,7 +417,7 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode, bool virt, bool hlvx if (pte & PTE_RSVD) { break; } else if (PTE_TABLE(pte)) { // next level of page table - if (pte & (PTE_D | PTE_A | PTE_U)) + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) break; base = ppn << PGSHIFT; } else if ((pte & PTE_U) ? s_mode && (type == FETCH || !sum) : !s_mode) { |