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| author | Chih-Min Chao <48193236+chihminchao@users.noreply.github.com> | 2021-08-04 19:19:38 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-08-04 04:19:38 -0700 |
| commit | 866b31ff9b05192965053a3b802967465febdeee (patch) | |
| tree | d0e219aa2d36b502f2a9b12988cf4be132f0d6fd /riscv/mmu.cc | |
| parent | c663ea20a53f4316db8cb4d591b1c8e437f4a0c4 (diff) | |
| download | riscv-isa-sim-866b31ff9b05192965053a3b802967465febdeee.zip riscv-isa-sim-866b31ff9b05192965053a3b802967465febdeee.tar.gz riscv-isa-sim-866b31ff9b05192965053a3b802967465febdeee.tar.bz2 | |
intr: make MIP_SEIP writable (#763)
based on riscv-privilege spec, section 3.1.9
"If supervisor mode is implemented, bits mip.SEIP and mie.SEIE are
the interrupt-pending and interrupt-enable bits for supervisor-level
external interrupts. SEIP is writable in mip, and may be written by M-mode
software to indicate to S-mode that an external interrupt is pending"
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'riscv/mmu.cc')
0 files changed, 0 insertions, 0 deletions