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| author | Andrew Waterman <andrew@sifive.com> | 2025-12-09 09:29:18 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-12-09 09:29:18 -0800 |
| commit | abb0d9873878268c0293edf20dcd8877f767a863 (patch) | |
| tree | 9abd2665300ea878d1ac85ee0e5676a74f181c17 /m4 | |
| parent | 59bf54676e0a2323bc5cb4a163fd3aca7f857ec3 (diff) | |
| parent | b4854c14934fda999f8d9b24ea692021c58787af (diff) | |
| download | riscv-isa-sim-master.zip riscv-isa-sim-master.tar.gz riscv-isa-sim-master.tar.bz2 | |
Fix VS-mode check for sireg* (really vsireg*) CSRs
Diffstat (limited to 'm4')
0 files changed, 0 insertions, 0 deletions