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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2026-04-07 00:46:22 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2026-04-29 02:35:21 -0700 |
| commit | f2aa295a31f6d0de376e807b2dfab5a62418c8dc (patch) | |
| tree | 11fcfc9c7014b82bc8d4b91123e85b6b8c5fd0a1 /m4 | |
| parent | 91a0debd84b16054dfa38ab38fbbcbfd1e52d9ec (diff) | |
| download | riscv-isa-sim-f2aa295a31f6d0de376e807b2dfab5a62418c8dc.tar.gz riscv-isa-sim-f2aa295a31f6d0de376e807b2dfab5a62418c8dc.tar.bz2 riscv-isa-sim-f2aa295a31f6d0de376e807b2dfab5a62418c8dc.zip | |
rvp: replace __int128 with int128_t/uint128_t and guard p-ext by HAVE_INT128
Replace bare __int128 / unsigned __int128 in psshar_dhs.h and psshar_dws.h
with the int128_t / uint128_t typedefs from fesvr/byteorder.h, and guard
the entire riscv_insn_ext_p list in riscv.mk.in with $(if $(HAVE_INT128),...)
matching the existing pattern for the V extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'm4')
0 files changed, 0 insertions, 0 deletions