diff options
| author | Ben Zong-You Xie <ben717@andestech.com> | 2025-12-29 15:19:14 +0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2026-02-11 12:14:04 +0530 |
| commit | b27ecec76b8acfece9c28078d02cbc6bc762135c (patch) | |
| tree | 4f792d1fff8cc1f21db663e02a048db3d658cbce /platform | |
| parent | 82b0961821e45768a91139b8ec5d7784586aa7f9 (diff) | |
| download | opensbi-b27ecec76b8acfece9c28078d02cbc6bc762135c.tar.gz opensbi-b27ecec76b8acfece9c28078d02cbc6bc762135c.tar.bz2 opensbi-b27ecec76b8acfece9c28078d02cbc6bc762135c.zip | |
lib: utils/suspend: add Andes ATCSMU suspend driver
Implement a system-wide suspend driver for the Andes AE350 platform.
This driver supports Andes-specific deep sleep (suspend to RAM) and
light sleep (suspend to standby) functionalities via the ATCSMU.
The major differences between deep sleep and light sleep are:
- Power Domain and Resume Path: Deep sleep powers down the core domain.
Consequently, harts waking from deep sleep resume from the reset
vector. Light sleep utilizes clock gating to the core domain; harts
maintain state and resume execution at the instruction immediately
following the WFI instruction.
- Primary Hart Wakeup: In both modes, the primary hart is woken by
UART or RTC alarm interrupts. In deep sleep, the primary hart is
additionally responsible for re-enabling the Last Level Cache (LLC)
and restoring Andes-specific CSRs.
- Secondary Hart Wakeup: In light sleep, secondary harts are woken
by an IPI sent from the primary hart. In deep sleep, they are
woken by an ATCSMU hardware wake-up command. Furthermore,
secondary harts must restore Andes-specific CSRs when returning
from deep sleep.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'platform')
| -rw-r--r-- | platform/generic/andes/ae350.c | 10 | ||||
| -rw-r--r-- | platform/generic/configs/defconfig | 1 |
2 files changed, 9 insertions, 2 deletions
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c index 9bd15543..4cf7e26d 100644 --- a/platform/generic/andes/ae350.c +++ b/platform/generic/andes/ae350.c @@ -8,9 +8,12 @@ #include <andes/andes_pmu.h> #include <andes/andes_sbi.h> #include <platform_override.h> +#include <sbi/sbi_ecall_interface.h> +#include <sbi/riscv_asm.h> #include <sbi/sbi_init.h> #include <sbi/sbi_scratch.h> #include <sbi_utils/fdt/fdt_helper.h> +#include <sbi_utils/hsm/fdt_hsm_andes_atcsmu.h> static unsigned long andes_hart_data_offset; extern void _start_warm(void); @@ -59,14 +62,17 @@ void ae350_enable_coherency_warmboot(void) static int ae350_early_init(bool cold_boot) { + u32 hartid = current_hartid(); + u32 sleep_type = atcsmu_get_sleep_type(hartid); + if (cold_boot) { andes_hart_data_offset = sbi_scratch_alloc_offset(sizeof(struct andes_hart_data)); if (!andes_hart_data_offset) return SBI_ENOMEM; } - /* Don't restore Andes CSRs during boot */ - if (sbi_init_count(current_hartindex())) + /* Don't restore Andes CSRs during boot or wake up from light sleep */ + if (sbi_init_count(current_hartindex()) && sleep_type == SBI_SUSP_SLEEP_TYPE_SUSPEND) ae350_non_ret_restore(sbi_scratch_thishart_ptr()); return generic_early_init(cold_boot); diff --git a/platform/generic/configs/defconfig b/platform/generic/configs/defconfig index 4b7615d6..19a73a24 100644 --- a/platform/generic/configs/defconfig +++ b/platform/generic/configs/defconfig @@ -62,6 +62,7 @@ CONFIG_FDT_SERIAL_UART8250=y CONFIG_FDT_SERIAL_XILINX_UARTLITE=y CONFIG_SERIAL_SEMIHOSTING=y CONFIG_FDT_SUSPEND=y +CONFIG_FDT_SUSPEND_ANDES_ATCSMU=y CONFIG_FDT_SUSPEND_RPMI=y CONFIG_FDT_SUSPEND_SIFIVE_SMC0=y CONFIG_FDT_TIMER=y |