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11 dayslib: utils/serial: Add support for Altera JTAG UARTIcenowy Zheng4-0/+127
Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/suspend: add Andes ATCSMU suspend driverBen Zong-You Xie4-8/+168
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add Andes last level cache controllerBen Zong-You Xie4-0/+184
Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add cache enable functionBen Zong-You Xie2-0/+34
Add functions to enable/disable the cache. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-4-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11platform: generic/andes: add CSR save and restore functions for AE350 platformBen Zong-You Xie1-0/+1
Implement a save and restore mechanism for Andes-specific CSRs to support hardware power-saving modes, such as CPU hotplug or suspend to RAM. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/hsm: factor out ATCSMU code into an HSM driverBen Zong-You Xie8-113/+181
Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: utils/serial: Support multiple UART8250 devicesBo Gan1-45/+59
Previously we assume only 1 UART8250 instance can be used. Now we support multiple instances by introducing counterpart functions to putc/getc/init which take an extra *dev parameter, and name them as uart8250_device_xyz() The original functions without the *dev parameter will operate on the default instance exactly the same as before, so no changes on the caller is required. Note: uart8250_device_init only does device initialization without the console registration logic. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils: Use SBI_DOMAIN_MMIO to check MMIO device permissionsSamuel Holland2-2/+3
Drivers or platforms may create memory regions with the MMIO flag set that contain S-mode-accessible MMIO devices. This is strictly correct and should be allowed, along with the existing default case of S-mode-accessible MMIO devices appearing in non-MMIO memory regions. When passed SBI_DOMAIN_MMIO, sbi_domain_check_addr() will perform the correct set of permission checks. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251121193808.1528050-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive Extensible Cache (EC) driverNick Hu3-0/+202
Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive PL2 controllerNick Hu3-0/+146
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()Nick Hu1-1/+3
The fdt_cache_add() helper attempts to retrieve the next-level cache and returns SBI_ENOENT when there is none. Since this condition only indicates that the current cache is the last-level cache, the helper should not treat it as an error. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-1-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/irqchip: plic: context_id is signedHeinrich Schuchardt1-2/+2
Array context_id in struct plic_data has elements of type s16. A negative valid indicates an invalid entry. Copying the array element to a u32 scalar hides the sign. Use s16 as target type when copying an array element to a scalar. Addresses-Coverity-ID: 1667176 Unsigned compared against 0 Addresses-Coverity-ID: 1667178 Logically dead code Addresses-Coverity-ID: 1667179 Unsigned compared against 0 Addresses-Coverity-ID: 1667182 Logically dead code Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251105110121.47130-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/serial: typo RecieveHeinrich Schuchardt1-1/+1
%s/Recieve/Receive/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251105011648.9413-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/timer: mtimer: add MIPS P8700 compatibleBenoît Monin1-0/+1
The MTIMER of the MIPS P8700 is compliant with the ACLINT specification, so add a compatible string for it. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107-p8700-aclint-v3-2-93eabb17d54e@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/timer: mtimer: Select the reference mtimer from a DT propertyBenoît Monin1-6/+10
The current selection of the reference MTIMER may fail in some setup. In a multi-cluster configuration, there is one MTIMER per cluster, each associated with the HARTS of the cluster. So we do not have a MTIMER with no associated HARTs to use as our reference. To be able to select a reference MTIMER in that case, look up an optional device tree property named "riscv,reference-mtimer" that indicate which MTIMER is the reference. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107-p8700-aclint-v3-1-93eabb17d54e@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-05lib: utils/ipi: mswi: add MIPS P8700 compatibleBenoît Monin1-0/+1
The MSWI present in the MIPS P8700 is compliant with the ACLINT specification, so add a dedicated compatible string for it. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251027-p8700-aclint-v2-1-f10cbfb66e92@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for performanceJoshua Yeong3-0/+98
Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for device powerJoshua Yeong3-0/+63
Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for voltageJoshua Yeong3-0/+84
Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/suspend: Add SiFive SMC0 driverNick Hu4-0/+382
The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/timer: Expose timer update functionNick Hu1-7/+21
Exposing the ACLINT timer update APIs so the user can update the mtimer after waking up from the non-retentive suspend. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-10-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/hsm: Add SiFive TMC0 driverNick Hu3-0/+318
The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/irqchip: Add APLIC restore functionNick Hu1-68/+96
Since the APLIC may enter a reset state upon system wake-up from a platform low power state, adding a restore function to reinitialize the APLIC. Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-7-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/cache: Add fdt cmo helpersNick Hu2-0/+115
Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28utils: cache: Add SiFive ccache controllerVincent Chen3-0/+186
SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add FDT cache libraryNick Hu4-0/+99
Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add cache flush libraryNick Hu4-0/+64
The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: utils/timer: mtimer: Add SiFive CLINT v2 supportYong-Xuan Wang1-0/+1
The SiFive CLINT v2 is the HRT that supports the Zicntr extension. It is incompatible with the SiFive CLINT v0 due to differences in their control methods. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250917105224.78291-1-yongxuan.wang@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: spacemit: Add HSM driverXianbin Zhu3-0/+147
Add code to bring up all 8 cores during OpenSBI initialization so that the Linux kernel can detect and use all cores properly. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-06lib: serial: sifive-uart: add shared memory region for SiFive UARTYu-Chien Peter Lin1-1/+4
Add shared memory region so the driver has permission to access it in OpenSBI. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250814111012.20151-1-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-30lib: utils/irqchip: fix aplic lock mechanism in xmsiaddrcfg(h)Yang Jialong1-7/+4
The section 4.5.4 "Supervisor MSI address configuration (smsiaddrcfg and smsiaddrcfgh)" of the AIA specification states that: "If register mmsiaddrcfgh of the domain has bit L set to one, then smsiaddrcfg and smsiaddrcfgh are locked as read-only alongside mmsiaddrcfg and mmsiaddrcfgh." In other words, the L bit is not defined for smsiaddrcfg[h] registers so fix aplic_writel_msicfg() accordingly. Signed-off-by: Yang Jialong <z_bajeer@yeah.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250806032924.3532975-1-z_bajeer@yeah.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: utils/ipi: Convert IPI drivers as early driversAnup Patel5-32/+4
The fdt_ipi_init() is already called from generic_early_init() so let's convert IPI drivers as early drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: sbi: Introduce IPI device ratingAnup Patel3-3/+6
A platform can have multiple IPI devices (such as ACLINT MSWI, AIA IMSIC, etc). Currently, OpenSBI rely on platform calling the sbi_ipi_set_device() function in correct order and prefer the first avaiable IPI device which is fragile. Instead of the above, introduce IPI device rating and prefer the highest rated IPI device. This further allows extending the sbi_ipi_raw_clear() to clear all available IPI devices. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Tested-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20250904052410.546818-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: utils/reset: Hang the hart after RPMI system reset messageRahul Pathak1-0/+3
RPMI system reset is a posted message which does not wait for acknowledgement after sending the RPMI message to PuC. Call the sbi_hart_hang() to hang the hart after performing the system reset via RPMI message. Fixes: 6a26726e08e4 ("lib/utils: reset: Add RPMI System Reset driver") Reported-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20250903144323.251270-1-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-23lib: utils: fdt: fix "ranges" translationMax Hsu1-11/+15
According to the Device Tree Spec, Chapter 2.3.8 "ranges" [1]: The parent address size will be determined from the #address-cells property of the node that defines the parent’s address space. In fdt_translate_address(), which considered the parent address size is the child address size, this commit fix the two address sizes and parsing the address independently. Signed-off-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250711-dev-maxh-master_fdt_helper-v2-1-9579e1f02ee1@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-07-20lib: utils/serial: Clear LSR status and check RBR statusYi Pei1-4/+3
On some platforms, read RBR when it is empty may result in an error. Signed-off-by: Yi Pei <neopimail@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/CAFPVDjQZ1gpf8-u--RBbAL1Y0FfDN2vZ3g=wBw+Bp-8ppuz3HA@mail.gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-24lib: rpmi: Make RPMI drivers as non-experimentalRahul Pathak7-7/+0
As RPMI v1.0 specification is frozen, disable the experimental tag for such RPMI drivers. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618053854.2577299-2-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-24lib: utils: Add Implementation ID and Version as RPMI MPXY attributesRahul Pathak2-0/+21
The latest frozen RPMI spec has added Implementation ID and Implementation Version as message protocol specific mpxy attributes. Add support for these. Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250618053854.2577299-1-rpathak@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: utils: Fix fdt_parse_aclint_node() for non-contiguous hartidAnup Patel1-3/+0
Currently, the fdt_parse_aclint_node() does not handle non-contiguous hartid correctly and returns incorrect first_hartid and hart_count. This is because the for-loop in fdt_parse_aclint_node() skips a hartid for which hartindex is not available (aka corresponding CPU DT node is disabled). For example, on a platform with 4 HARTs (hartid 0, 1, 2, and 3) where CPU DT nodes with hartid 0 and 2 are disabled, the fdt_parse_aclint_node() returns first_hartid = 1 and hart_count = 3 which is incorrect. To address the above issue, drop the sbi_hartid_to_hartindex() check from the for-loop of fdt_parse_aclint_node(). Fixes: 5e90e54a1a53 ("lib: utils:Check that hartid is valid") Reported-by: Maria Mbaye <MameMaria.Mbaye@microchip.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250606055810.237441-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-16lib: utils/irqchip: always parse msi information for each aplic deviceInochi Amaoto1-69/+71
OpenSBI only parses MSI information of the first next level subdomain for now, which makes the root domain misconfigured in some case: 1. the msi is not enabled on the first subdomain of the root domain, but other subdomains enable MSI. 2. the root domain is set as direct mode, but its subdomains enable MSI. So it is needed to parse all child of the root domain, Otherwise, the some non-root domains are broken. As the specification says, it is safe to parse the MSI information of all its subdomain and write the msiaddrcfg register of the non root domain as they are read only. Parse the aplic MSI information recursively for all aplic device. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/r/20250523085348.1690368-1-inochiama@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-06-14lib: utils: hsm: Do not fail on EALREADY in rpmi-hsm fixup.Ziang Wang1-1/+1
In case harts are divided into groups that use different rpmi-hsm channels in different mailboxes, the suspend state fixup function will return EALREADY on secondary entry, simply skip on this error. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com> Link: https://lore.kernel.org/r/20250507074620.3162747-1-wangziang.ok@bytedance.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils: fdt: Claim Zicntr if time CSR emulation is possibleYao Zi1-1/+32
OpenSBI is capable of emulating time CSR through an external timer for HARTs that don't implement a full Zicntr extension. Let's add Zicntr extension in the FDT if CSR emulation is active. This avoids hardcoding the extension in the devicetree, which may confuse pre-SBI bootloaders. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250516133352.36617-4-ziyao@disroot.org Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils: Fix fdt_mpxy_init() not returning error codeAlvin Chang1-6/+2
It seems that current implementation doesn't fail on fdt_mpxy_init(), because platforms might not have any MPXY devices. In fact, if there are no MPXY devices, fdt_driver_init_all() will return SBI_OK. More importantly, if there is any MPXY device which fails the initialization, OpenSBI must check the error code and stop the booting. Thus, this commit adds the return value for fdt_mpxy_init(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250430091007.3768180-1-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mpxy: Remove p2a_db_index from RPMI system MSI attributesAnup Patel1-4/+9
The discovery of P2A doorbell system MSI index is now through RPMI shared memory DT node so remove p2a_db_index from RPMI system MSI attributes and access it as a mailbox channel attribute. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Parse A2P doorbell value from DTAnup Patel1-4/+10
The A2P doorbell value written to the 32-bit A2P doorbell value must be discoverd from device tree instead of always using the default value 1. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Parse P2A doorbell system MSI index from DTAnup Patel1-4/+12
The P2A doorbell system MSI index is expected to be discovered from device tree instead of RPMI system MSI service group attribute. This is based on ARC feedback before RPMI spec was frozen. Let's parse P2A doorbell system MSI index from device tree and also expose it as rpmi channel attribute to RPMI client drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Update DT register name of A2P doorbellAnup Patel1-2/+2
The latest device tree bindings define A2P doorbell register name as "a2p-doorbell" so update rpmi_shmem_transport_init() accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-24lib: sbi: Set the scratch allocation to alignment to cacheline sizeRaj Vishwanathan1-0/+24
Set the scratch allocation alignment to cacheline size specified by riscv,cbom-block-size in the DTS file to avoid two atomic variables from the same cache line causing livelock on some platforms. If the cacheline is not specified, we set it a default value. Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: utils/fdt: Remove fdt_match_node()Samuel Holland1-19/+0
This function has been obsoleted by the fdt_driver library and is no longer used. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-10-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-15lib: sbi: Remove unnecessary SBI_INIT_LIST_HEADXiang W2-3/+0
No need to initialise the nodes to be added to the linked list Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250319123944.505756-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2026-03-03 04:48:13 +0000