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2026-04-08lib: sbi_bitmap_test: add tests for bitmap_empty()HEADmasterYu-Chien Peter Lin1-0/+29
Add tests for bitmap_empty(), covers empty/non-empty bitmaps and edge case nbits=0. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260311125116.1401002-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: utils: Add MPXY client driver for RPMI MM service groupRanbir Singh3-0/+123
Add necessary infra for implementing RPMI Management Mode service group on platform microcontroller. Co-authored-by: Sunil V L <sunilvl@oss.qualcomm.com> Signed-off-by: Ranbir Singh <ranbir.singh@oss.qualcomm.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260225061347.1396504-1-ranbir.singh@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: Fix sbi_strchr to correctly handle null terminator searchChen Pei1-6/+5
The original sbi_strchr implementation did not conform to the C standard behavior. According to the C standard and POSIX specification, strchr(s, 0) should return a pointer to the null terminator at the end of string s. The previous implementation used a while loop that would terminate when either reaching the end of string or finding the character, but it would return NULL when searching for the null terminator instead of returning a pointer to the null terminator itself. The fixed implementation uses a do-while loop that ensures even when searching for the null terminator, the function correctly returns a pointer to the null terminator position rather than NULL. This fix ensures sbi_strchr behavior aligns with standard library function semantics, making it more predictable and safe for users expecting standard C library behavior. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260306094425.1918-3-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-04-06lib: tests: Add test for stringChen Pei2-0/+375
Added unit tests for various string operations using SBI unit test framework. Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260306094425.1918-2-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_init: Call hart init and timer init before platform early initYu-Chien Peter Lin1-14/+12
To allow the platform early drivers to use the sbi_timer_mdelay(), sbi_timer_udelay() and sbi_hart_has_extension() helpers, reorder the initialization sequence must call sbi_hart_init() and sbi_timer_init() prior to sbi_platform_early_init() during both cold and warm boot paths. Reviewed-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Link: https://lore.kernel.org/r/20260224031733.3817148-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Allow registering interrupt handlersAnup Patel4-2/+212
To handle external interrupts in M-mode, the sbi_irqchip framework must allow registering interrupt handlers from device drivers. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Associate 32-bit unique ID for each irqchip deviceAnup Patel4-0/+18
Allow locating irqchip device instance using a unique 32-bit ID. This 32-bit unique ID can be set by the irqchip driver at the time of adding irqchip device. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-8-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add unique_id to plic, aplic, and imsic dataAnup Patel1-0/+3
Add a 32-bit unique ID to plic, aplic, and imsic data which can be used to differentiate multiple irqchip devices. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-7-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Support irqchip device targetting subset of hartsAnup Patel4-20/+67
It is possible to have platform where an irqchip device targets a subset of harts and there are multiple irqchip devices to cover all harts. To support this scenario: 1) Add target_harts hartmask to struct sbi_irqchip_device which represents the set of harts targetted by the irqchip device 2) Call warm_init() and process_hwirqs() callbacks of an irqchip device on a hart only if irqchip device targets that particular hart Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-6-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Add IDC to hartindex map in struct aplic_dataAnup Patel1-1/+53
A platform can have multiple APLICs in direct-mode targetting different subset of harts. Add APLIC ID to hartindex map in struct aplic_data to capture the set of harts targeted by a given APLIC in direct-mode. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-5-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: utils/irqchip: Fix context_map init in irqchip_plic_update_context_map()Anup Patel1-0/+5
The context_map[][] elements should be initialized with negative value so that context_map does not point to anything for non-existent PLIC contexts. Fixes: 69448a079065 ("lib: utils/irqchip: plic: Provide a hartindex to context map") Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-4-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Rename irq_handle() callback to process_hwirqs()Anup Patel2-4/+4
The irq_handle() callback of irqchip device is meant to process hardware interrupt of the irqchip hence rename it accordingly. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-3-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-22lib: sbi_irqchip: Use chip as variable name for irqchip deviceAnup Patel1-8/+8
The irqchip device represents an interrupt controller so use chip as variable name instead of dev. This will avoid confusion as the sbi_irqchip framework grows. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260213055342.3124872-2-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-10lib: sbi: fix sse_event_inject() status settingCharlie Jenkins1-1/+1
sse_event_inject() currently sets all status bits to 1 except for SBI_SSE_ATTR_STATUS_PENDING_OFFSET which it sets to zero. Instead of overwriting all the values of the status bits, sse_event_inject() is only expected to clear SBI_SSE_ATTR_STATUS_PENDING_OFFSET. Fix sse_event_inject() to only do the clearing. Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260302-event_inject_fix-v1-1-e88952b03aa4@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-10lib: Use proper add opcode on RV32 with ZalrscMarti Alonso2-1/+5
The addw opcode is only defined in RV64, which produces 32-bit results. On RV32, the default add opcode already produces 32-bit results. Fixes: 995f226f3f33 ("lib: Emit lr and sc instructions based on -march flags") Signed-off-by: Marti Alonso <martialonso11@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260301205421.2074835-1-martialonso11@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09lib: fdt_helper: Removed unnecessary dt parsing checkVictoriano Morales1-4/+4
The check for the address being different from 0 for the UART, PLIC, APLIC and IMSIC dt nodes is unnnecessary and could skip valid nodes. Signed-off-by: Victoriano Morales <victoriano.morales@openchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260219083423.30690-1-victoriano.morales@openchip.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-03-09lib: sbi: Fix undefined behavior in signed shifts in sbi_hart.cMarcos Oduardo1-1/+1
UBSan detected undefined behavior in sbi_hart.c and sbi_fwft.c (in the case of sbi_fwft.c, the bug comes from a macro call defined at sbi_ecall_interface.h) caused by shifting a signed integer into the sign bit (1 << 31) This can be fixed by using the 1UL literal, ensuring defined arithmetic. Please let me know if there’s any other most suitable solution for this bug. Signed-off-by: Marcos Oduardo <marcos.oduardo@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223001202.284612-1-marcos.oduardo@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25lib: sbi_hart_pmp: disable unconfigured PMP entriesVladimir Kondratiev1-0/+6
Disable PMP entries not configured in domain. These entries may contain values configured by the boot loader; disabling it to be certain PMP configuration is exactly as configured by the openSBI Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-2-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-25lib: sbi: print hartid in hexVladimir Kondratiev1-1/+1
Hartid is better represented by hex number since it is likely a combination of bits representing various elements in the platform hierarchy Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260223-for-upstream-eyeq7h-v3-1-621d004d1a21@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-21lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64James Raphael Tiovalen2-3/+11
Currently, when we attempt to read the upper 32 bits of a firmware counter on RV64 or higher, we just set `sbiret.value` to 0 without validating the counter index. The SBI specification requires us to set `sbiret.error` to `SBI_ERR_INVALID_PARAM` if the counter index points to a hardware counter or an invalid counter. Add a validation check to ensure compliance with the specification on RV64 or higher. Fixes: 51951d9e9af8 ("lib: sbi_pmu: Implement sbi_pmu_counter_fw_read_hi") Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260125090643.190748-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20lib: sbi_pmu: Fix multiple FW counter start operations with custom PMU deviceJames Raphael Tiovalen1-1/+5
Currently, we immediately return the result of `fw_counter_start` if the event code is 0xFFFF. However, this skips setting the bit in the `fw_counters_started` bitmap even if the platform-specific call succeeds. Restore the original behavior of returning early only on an error so that we still set the bit in the bitmap. This prevents multiple starts of the same FW counter. This also aligns the expectations of `pmu_ctr_start_fw` with `pmu_ctr_stop_fw` since we cannot assume that the platform-specific functions to start and stop FW counters will modify the bitmap state. Fixes: 57d3aa3b0dbd ("lib: sbi_pmu: Introduce fw_counter_write_value API") Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260116165304.180441-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-20lib: utils/serial: Add support for Altera JTAG UARTIcenowy Zheng4-0/+127
Altera provides a JTAG UART core that provides virtual UART over JTAG and can coexist with their virtual JTAG. [1] This core has already been supported by Linux and the programming interface has always been stable. Add support for it to OpenSBI to ease JTAG prototype bringing up. The driver follows the device tree binding in mainline Linux. [2] [1] https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/jtag-uart-core [2] https://github.com/torvalds/linux/blob/v6.19-rc1/Documentation/devicetree/bindings/serial/altr%2Cjuart-1.0.yaml Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20260104065506.70182-1-zhengxingda@iscas.ac.cn Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/suspend: add Andes ATCSMU suspend driverBen Zong-You Xie4-8/+168
Implement a system-wide suspend driver for the Andes AE350 platform. This driver supports Andes-specific deep sleep (suspend to RAM) and light sleep (suspend to standby) functionalities via the ATCSMU. The major differences between deep sleep and light sleep are: - Power Domain and Resume Path: Deep sleep powers down the core domain. Consequently, harts waking from deep sleep resume from the reset vector. Light sleep utilizes clock gating to the core domain; harts maintain state and resume execution at the instruction immediately following the WFI instruction. - Primary Hart Wakeup: In both modes, the primary hart is woken by UART or RTC alarm interrupts. In deep sleep, the primary hart is additionally responsible for re-enabling the Last Level Cache (LLC) and restoring Andes-specific CSRs. - Secondary Hart Wakeup: In light sleep, secondary harts are woken by an IPI sent from the primary hart. In deep sleep, they are woken by an ATCSMU hardware wake-up command. Furthermore, secondary harts must restore Andes-specific CSRs when returning from deep sleep. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-6-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add Andes last level cache controllerBen Zong-You Xie4-0/+184
Introduce a FDT-based driver for the Andes Last Level Cache (LLC) controller to support cache maintenance operations. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-5-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/cache: add cache enable functionBen Zong-You Xie2-0/+34
Add functions to enable/disable the cache. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-4-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11platform: generic/andes: add CSR save and restore functions for AE350 platformBen Zong-You Xie1-0/+1
Implement a save and restore mechanism for Andes-specific CSRs to support hardware power-saving modes, such as CPU hotplug or suspend to RAM. Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-3-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-02-11lib: utils/hsm: factor out ATCSMU code into an HSM driverBen Zong-You Xie8-113/+181
Refactor ATCSMU (System Management Unit) support by moving it from a system utility into a dedicated FDT-based HSM driver. Key changes include: - Moving the functions in lib/utils/sys/atcsmu.c into the new HSM driver - Moving hart start and stop operations on AE350 platform into the new HSM driver - Converting the assembly-based functions in sleep.S to C code for the readability - Updating the ATCWDT200 driver Signed-off-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Link: https://lore.kernel.org/r/20251229071914.1451587-2-ben717@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2026-01-08lib: sbi: Fix behavior on platform without HART protectionv1.8.1release-1.8.xMichal Simek1-7/+3
The commit 42139bb9b7dc ("lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()") changed logic by calling sbi_hart_protection_configure(). But when protection doesn't exist the function is returning SBI_EINVAL. But on systems without protection this is correct configuration that's why do not hang when system don't have any HART protection. Fixes: 42139bb9b7dc ("lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()") Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/bb8641e5f82654e3989537cea85f165f67a7044e.1767801896.git.michal.simek@amd.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-28lib: atomics: fix AMO test macrosVladimir Kondratiev3-15/+15
The "RISC-V C API" [1] defines architecture extension test macros says naming rule for the test macros is __riscv_<ext_name>, where <ext_name> is all lower-case. Three extensions dealing with atomics implementation are: "zaamo" consists of AMO instructions, "zalrsc" - LR/SC, "a" extension means both "zaamo" and "zalrsc" Built-in test macros are __riscv_a, __riscv_zaamo and __riscv_zalrsc. Alternative to the __riscv_a macro name, __riscv_atomic, is deprecated. Use correct test macro __riscv_zaamo for the AMO variant of atomics. It used to be __riscv_atomic that is both deprecated and incorrect because it tests for the "a" extension; i.e. both "zaamo" and "zalrsc" If ISA enables only zaamo but not zalrsc, code as it was would not compile. Older toolchains may have neither __riscv_zaamo nor __riscv_zalrsc, so query __riscv_atomic - it should be treated as both __riscv_zaamo and __riscv_zalrsc, in all present cases __riscv_zaamo is more favorable so take is as alternative for __riscv_zaamo [1] https://github.com/riscv-non-isa/riscv-c-api-doc Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251228073321.1533844-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-27lib: sbi_pmu: Fix multiple start and stop operations of FW countersJames Raphael Tiovalen1-0/+6
Currently, OpenSBI returns SBI_ERR_ALREADY_STARTED when attempting to start a HW counter that is already started and SBI_ERR_ALREADY_STOPPED when attempting to stop a HW counter that is already stopped. However, this is not yet implemented for FW counters. Add the necessary checks to return the same error codes when attempting the same actions on FW counters. Signed-off-by: James Raphael Tiovalen <jamestiotio@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251213104146.422972-1-jamestiotio@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-27lib/sbi: optimize domain memory regions copyingVladimir Kondratiev1-15/+5
There are 2 locations where memory regions moved in a bulk, but this implemented in a region-by region move or even swap. Use more effective way. Note, last entry, dom->regions[count], always exists and is empty, copying it replaces clear_region() Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20251208125617.2557594-1-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-26lib: sbi: expected trap must always clear MPRVDeepak Gupta1-0/+4
Expected trap must always clear MPRV. Currently it doesn't. There is a security issue here where if firmware was doing ld/st with MPRV=1 and since there would be a expected trap, opensbi will continue to run as MPRV=1. Security impact is DoS where opensbi will just keep trapping. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251124220339.3695940-1-debug@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: utils/serial: Support multiple UART8250 devicesBo Gan1-45/+59
Previously we assume only 1 UART8250 instance can be used. Now we support multiple instances by introducing counterpart functions to putc/getc/init which take an extra *dev parameter, and name them as uart8250_device_xyz() The original functions without the *dev parameter will operate on the default instance exactly the same as before, so no changes on the caller is required. Note: uart8250_device_init only does device initialization without the console registration logic. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-7-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi: give platform choice of using single memregion to cover OpenSBIBo Gan1-12/+24
By default the OpenSBI itself is covered by 2 memregions for RX/RW sections. This is required by platforms with Smepmp to enforce proper permissions in M mode. Note: M-mode only regions can't have RWX permissions with Smepmp. Platforms with traditional PMPs won't be able to benefit from it, as both regions are effectively RWX in M mode, but usually it's harmless to so. Now we provide these platforms with an option to disable this logic. It saves 1 PMP entry. For platforms really in short of PMPs, it does make a difference. Note: Platform requesting single OpenSBI memregion must be using traditional (old) PMP. We expect the platform code to do the right thing. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-5-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_domain: make is_region_subset publicBo Gan1-20/+3
The helper function is renamed as sbi_domain_memregion_is_subset, and made public in header file. Also add a convenient helper of sbi_domain_for_each_memregion_idx. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-4-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_domain: add sbi_domain_get_oldpmp_flagsBo Gan2-16/+23
Factor out logic in `sbi_hart_oldpmp_configure` into function `sbi_domain_get_oldpmp_flags`, analogous to `sbi_domain_get_smepmp_flags`. Platform specific hart-protection implementation can now leverage it. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-3-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-21lib: sbi_hart_pmp: make sbi_hart_pmp_fence publicBo Gan1-1/+1
sbi_hart_pmp_fence can now be utilized by other hart-protection implementation. Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251218104243.562667-2-ganboing@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Flush TLBs upon FWFT ADUE changeAndrew Waterman1-1/+12
A clarification has been added to the RISC-V privileged specification regarding synchronization requirements when xenvcfg.ADUE changes. (Refer, the following commit in the RISC-V Privileged ISA spec https://github.com/riscv/riscv-isa-manual/commit/4e540263db8ae3a27d132a1752cc0fad222facd8) As-per these requirements, the SBI FWFT ADUE implementation must flush TLBs upon changes in ADUE state on a hart. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251127112121.334023-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Expose __sbi_sfence_vma_all() functionAndrew Waterman2-3/+4
The __sbi_sfence_vma_all() can be shared by different parts of OpenSBI so rename __tlb_flush_all() to __sbi_sfence_vma_all() and make it global function. Signed-off-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251127112121.334023-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Factor-out PMP programming into separate sourcesAnup Patel4-332/+359
The PMP programming is a significant part of sbi_hart.c so factor-out this into separate sources sbi_hart_pmp.c and sbi_hart_pmp.h for better maintainability. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-6-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Replace sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr()Anup Patel8-77/+56
The sbi_hart_pmp_xyz() and sbi_hart_map/unmap_addr() functions can now be replaced by various sbi_hart_protection_xyz() functions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Implement hart protection for PMP and ePMPAnup Patel1-76/+132
Implement PMP and ePMP based hart protection abstraction so that usage of sbi_hart_pmp_xyz() functions can be replaced with sbi_hart_protection_xyz() functions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Introduce hart protection abstractionAnup Patel3-0/+102
Currently, PMP and ePMP are the only hart protection mechanisms available in OpenSBI but new protection mechanisms (such as Smmpt) will be added in the near future. To allow multiple hart protection mechanisms, introduce hart protection abstraction and related APIs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-16lib: sbi: Introduce sbi_hart_pmp_unconfigure() functionAnup Patel2-9/+15
Currently, the unconfiguring PMP is implemented directly inside switch_to_next_domain_context() whereas rest of the PMP programming is done via functions implemented in sbi_hart.c. Introduce a separate sbi_hart_pmp_unconfigure() function so that all PMP programming is in one place. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20251209135235.423391-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils: Use SBI_DOMAIN_MMIO to check MMIO device permissionsSamuel Holland2-2/+3
Drivers or platforms may create memory regions with the MMIO flag set that contain S-mode-accessible MMIO devices. This is strictly correct and should be allowed, along with the existing default case of S-mode-accessible MMIO devices appearing in non-MMIO memory regions. When passed SBI_DOMAIN_MMIO, sbi_domain_check_addr() will perform the correct set of permission checks. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251121193808.1528050-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: sbi_domain: Allow MMIO access to non-MMIO rangesSamuel Holland1-1/+5
Currently, platforms do not provide complete memory region information to OpenSBI. Generally, memory regions are only created for the few MMIO devices that have M-mode drivers. As a result, most MMIO devices fall inside the default S-mode RWX memory region, which does _not_ have the MMIO flag set. In fact, OpenSBI relies on certain S-mode MMIO devices being inside non-MMIO memory regions. Both fdt_domain_based_fixup_one() and mpxy_rpmi_sysmis_xfer() call sbi_domain_check_addr() with the MMIO flag cleared, and that function currently requires an exact flag match. Those access checks will thus erroneously fail if the platform creates memory regions with the correct flags for these devices (or for a larger MMIO region containing these devices). We should not ignore the MMIO flag entirely, because sbi_domain_check_addr() is also used to check the permissions of S-mode shared memory buffers, and S-mode should not be using MMIO device addresses as memory buffers. But when checking if S-mode is allowed to do MMIO accesses, we need to recognize that MMIO devices appear in memory regions both with and without the MMIO flag set. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251121193808.1528050-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: sbi: Enable Ssqosid Ext using mstateen0Chen Pei2-0/+10
The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual Changes in v5: - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12 Changes in v4: - Remove extraneous parentheses around SMSTATEEN0_SRMCFG Changes in v3: - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG Changes in v2: - Remove trap-n-detect - Context switch CSR_SRMCFG Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive Extensible Cache (EC) driverNick Hu3-0/+202
Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive PL2 controllerNick Hu3-0/+146
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()Nick Hu1-1/+3
The fdt_cache_add() helper attempts to retrieve the next-level cache and returns SBI_ENOENT when there is none. Since this condition only indicates that the current cache is the last-level cache, the helper should not treat it as an error. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-1-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
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