aboutsummaryrefslogtreecommitdiff
path: root/lib
AgeCommit message (Collapse)AuthorFilesLines
2025-12-08lib: utils: Use SBI_DOMAIN_MMIO to check MMIO device permissionsHEADmasterSamuel Holland2-2/+3
Drivers or platforms may create memory regions with the MMIO flag set that contain S-mode-accessible MMIO devices. This is strictly correct and should be allowed, along with the existing default case of S-mode-accessible MMIO devices appearing in non-MMIO memory regions. When passed SBI_DOMAIN_MMIO, sbi_domain_check_addr() will perform the correct set of permission checks. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251121193808.1528050-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: sbi_domain: Allow MMIO access to non-MMIO rangesSamuel Holland1-1/+5
Currently, platforms do not provide complete memory region information to OpenSBI. Generally, memory regions are only created for the few MMIO devices that have M-mode drivers. As a result, most MMIO devices fall inside the default S-mode RWX memory region, which does _not_ have the MMIO flag set. In fact, OpenSBI relies on certain S-mode MMIO devices being inside non-MMIO memory regions. Both fdt_domain_based_fixup_one() and mpxy_rpmi_sysmis_xfer() call sbi_domain_check_addr() with the MMIO flag cleared, and that function currently requires an exact flag match. Those access checks will thus erroneously fail if the platform creates memory regions with the correct flags for these devices (or for a larger MMIO region containing these devices). We should not ignore the MMIO flag entirely, because sbi_domain_check_addr() is also used to check the permissions of S-mode shared memory buffers, and S-mode should not be using MMIO device addresses as memory buffers. But when checking if S-mode is allowed to do MMIO accesses, we need to recognize that MMIO devices appear in memory regions both with and without the MMIO flag set. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251121193808.1528050-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: sbi: Enable Ssqosid Ext using mstateen0Chen Pei2-0/+10
The QoS Identifiers extension (Ssqosid) introduces the srmcfg register, which configures a hart with two identifiers: a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). These identifiers accompany each request issued by the hart to shared resource controllers. If extension Smstateen is implemented together with Ssqosid, then Ssqosid also requires the SRMCFG bit in mstateen0 to be implemented. If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes less privileged than M-mode raise an illegal-instruction exception. If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented, attempts to access srmcfg when V=1 raise a virtual-instruction exception. This extension can be found in the RISC-V Instruction Set Manual: https://github.com/riscv/riscv-isa-manual Changes in v5: - Remove SBI_HART_EXT_SSQOSID dependency SBI_HART_PRIV_VER_1_12 Changes in v4: - Remove extraneous parentheses around SMSTATEEN0_SRMCFG Changes in v3: - Check SBI_HART_EXT_SSQOSID when swapping SRMCFG Changes in v2: - Remove trap-n-detect - Context switch CSR_SRMCFG Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Reviewed-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20251114115722.1831-1-cp0613@linux.alibaba.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive Extensible Cache (EC) driverNick Hu3-0/+202
Add support for SiFive Extensible Cache (EC) controller with multi-slice architecture. The driver implements cache maintenance operations through MMIO register interface. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-3-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Add SiFive PL2 controllerNick Hu3-0/+146
SiFive Private L2(PL2) cache is a private cache owned by each hart. Add this driver to support private cache flush operations via the MMIO registers. Co-developed-by: Eric Lin <eric.lin@sifive.com> Signed-off-by: Eric Lin <eric.lin@sifive.com> Co-developed-by: Zong Li <zong.li@sifive.com> Signed-off-by: Zong Li <zong.li@sifive.com> Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-2-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-08lib: utils/cache: Handle last-level cache correctly in fdt_cache_add()Nick Hu1-1/+3
The fdt_cache_add() helper attempts to retrieve the next-level cache and returns SBI_ENOENT when there is none. Since this condition only indicates that the current cache is the last-level cache, the helper should not treat it as an error. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251114-sifive-cache-drivers-v1-1-8423a721924c@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-02lib: sbi: Remove static variable root_memregs_countVladimir Kondratiev1-4/+14
Calculate number of used memory regions using helper function when needed. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251111104327.1170919-3-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-02lib: sbi: fix covered regions handling in sanitize_domain()Vladimir Kondratiev1-1/+1
In the sanitize_domain, code that checks for the case when one memory region covered by the other, was never executed. Quote: /* Sort the memory regions */ for (i = 0; i < (count - 1); i++) { <snip> } /* Remove covered regions */ while(i < (count - 1)) { Here "while" loop never executed because condition "i < (count - 1)" is always false after the "for" loop just above. In addition, when clearing region, "root_memregs_count" should be adjusted as well, otherwise code that adds memory region in the "root_add_memregion" will use wrong position: /* Append the memregion to root memregions */ nreg = &root.regions[root_memregs_count]; empty entry will be created in the middle of regions array, new regions will be added after this empty entry while sanitizing code will stop when reaching empty entry. Fixes: 3b03cdd60ce5 ("lib: sbi: Add regions merging when sanitizing domain region") Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251111104327.1170919-2-vladimir.kondratiev@mobileye.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-12-01lib: sbi_pmu: Fix xINH bits configuringShifrin Dmitry1-7/+26
Before this patch sbi_pmu_ctr_start() ignores flags received in sbi_pmu_ctr_cfg_match() including inhibit ones. To prevent it, save flags together with event_data and use them both in sbi_pmu_ctr_start(). Fixes: 1db95da2997b ("lib: sbi: sbi_pmu: fixed hw counters start for hart") Signed-off-by: Shifrin Dmitry <dmitry.shifrin@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251110113140.80561-1-dmitry.shifrin@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/irqchip: plic: context_id is signedHeinrich Schuchardt1-2/+2
Array context_id in struct plic_data has elements of type s16. A negative valid indicates an invalid entry. Copying the array element to a u32 scalar hides the sign. Use s16 as target type when copying an array element to a scalar. Addresses-Coverity-ID: 1667176 Unsigned compared against 0 Addresses-Coverity-ID: 1667178 Logically dead code Addresses-Coverity-ID: 1667179 Unsigned compared against 0 Addresses-Coverity-ID: 1667182 Logically dead code Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251105110121.47130-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/serial: typo RecieveHeinrich Schuchardt1-1/+1
%s/Recieve/Receive/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251105011648.9413-1-heinrich.schuchardt@canonical.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/timer: mtimer: add MIPS P8700 compatibleBenoît Monin1-0/+1
The MTIMER of the MIPS P8700 is compliant with the ACLINT specification, so add a compatible string for it. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107-p8700-aclint-v3-2-93eabb17d54e@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-10lib: utils/timer: mtimer: Select the reference mtimer from a DT propertyBenoît Monin1-6/+10
The current selection of the reference MTIMER may fail in some setup. In a multi-cluster configuration, there is one MTIMER per cluster, each associated with the HARTS of the cluster. So we do not have a MTIMER with no associated HARTs to use as our reference. To be able to select a reference MTIMER in that case, look up an optional device tree property named "riscv,reference-mtimer" that indicate which MTIMER is the reference. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251107-p8700-aclint-v3-1-93eabb17d54e@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-05lib: utils/ipi: mswi: add MIPS P8700 compatibleBenoît Monin1-0/+1
The MSWI present in the MIPS P8700 is compliant with the ACLINT specification, so add a dedicated compatible string for it. Signed-off-by: Benoît Monin <benoit.monin@bootlin.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251027-p8700-aclint-v2-1-f10cbfb66e92@bootlin.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for performanceJoshua Yeong3-0/+98
Add MPXY RPMI mailbox driver for performance. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-4-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for device powerJoshua Yeong3-0/+63
Add MPXY RPMI mailbox driver for device power. Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-3-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-04lib: utils: Add MPXY RPMI mailbox driver for voltageJoshua Yeong3-0/+84
Add voltage service group for RPMI/MPXY support Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com> Reviewed-by: Rahul Pathak <rpathak@ventanamicro.com> Link: https://lore.kernel.org/r/20251013153138.1574512-2-joshua.yeong@starfivetech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain_context: preserve firmware PMP entries during domain context ↵Yu-Chien Peter Lin1-0/+4
switch When SmePMP is enabled, clearing firmware PMP entries during a domain context switch can temporarily revoke access to OpenSBI’s own code and data, leading to faults. Keep firmware PMP entries enabled across switches so firmware regions remain accessible and executable. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-9-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi: sbi_hart: track firmware PMP entries for SmePMPYu-Chien Peter Lin1-0/+29
Add fw_smepmp_ids bitmap to track PMP entries that protect firmware regions. Allow us to preserve these critical entries across domain transitions and check inconsistent firmware entry allocation. Also add sbi_hart_smepmp_is_fw_region() helper function to query whether a given SmePMP entry protects firmware regions. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-8-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: ensure consistent firmware PMP entriesYu-Chien Peter Lin1-0/+13
During domain context switches, all PMP entries are reconfigured which can clear firmware access permissions, causing M-mode access faults under SmePMP. Sort domain regions to place firmware regions first, ensuring consistent firmware PMP entries so they won't be revoked during domain context switches. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-7-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: add SBI_DOMAIN_MEMREGION_FW memregion flagYu-Chien Peter Lin1-2/+6
Add a new memregion flag, SBI_DOMAIN_MEMREGION_FW and mark the OpenSBI code and data regions. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-6-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_hart: return error when insufficient PMP entries availableYu-Chien Peter Lin1-6/+15
Previously, when memory regions exceed available PMP entries, some regions were silently ignored. If the last entry that covers the full 64-bit address space is not added to a domain, the next stage S-mode software won't have permission to access and fetch instructions from its memory. So return early with error message to catch such situation. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-5-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: print unsupported SmePMP permissionsYu-Chien Peter Lin1-0/+6
The reg->flag is encoded with 6 bits to specify RWX permissions for M-mode and S-/U-mode. However, only 16 of the possible encodings are valid on SmePMP. Add a warning message when an unsupported permission encoding is detected. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-4-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_domain: allow specifying inaccessible regionYu-Chien Peter Lin2-5/+11
According to the RISC‑V Privileged Specification, SmePMP regions that grant no access in any privilege mode are valid. Allow such regions to be specified. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-3-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-11-02lib: sbi_hart: move sbi_hart_get_smepmp_flags() to sbi_domainYu-Chien Peter Lin2-65/+60
Move sbi_hart_get_smepmp_flags() from sbi_hart.c to sbi_domain.c and rename it to sbi_domain_get_smepmp_flags() to better reflect its purpose of converting domain memory region flags to PMP configuration. Also removes unused parameters (scratch and dom). Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251008084444.3525615-2-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/suspend: Add SiFive SMC0 driverNick Hu4-0/+382
The SiFive SMC0 controls the clock and power domain of the core complex on the SiFive platform. The core complex enters the low power state after the secondary cores enter the tile power gating and last core execute the `CEASE` instruction with the corresponding SMC0 configurations. The devices that inside both tile power domain and core complex power domain will be off, including caches and timer. Therefore we need to flush the last level cache before entering the core complex power gating and update the timer after waking up. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-12-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add system_resume callback for restoring the systemNick Hu2-1/+21
The last core who performs the system suspend is responsible for restoring the system after waking up. Add the system_resume callback for restoring the system from suspend. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-11-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/timer: Expose timer update functionNick Hu1-7/+21
Exposing the ACLINT timer update APIs so the user can update the mtimer after waking up from the non-retentive suspend. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-10-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/hsm: Add SiFive TMC0 driverNick Hu3-0/+318
The SiFive TMC0 controls the tile power domains on SiFive platform. The CPU enters the low power state via the `CEASE` instruction after configuring the TMC0. Any devices that inside the tile power domain will be power gated, including the private cache. Therefore flushing the private cache before entering the low power state. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-9-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Extends sbi_ipi_raw_send() to use all available IPI devicesNick Hu2-4/+14
A platform may contain multiple IPI devices. In certain use cases, such as power management, it may be necessary to send an IPI through a specific device to wake up a CPU. For example, if an IMSIC is powered down and reset, the core cannot receive IPIs from it, so the wake-up must instead be triggered through the CLINT. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-8-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/irqchip: Add APLIC restore functionNick Hu1-68/+96
Since the APLIC may enter a reset state upon system wake-up from a platform low power state, adding a restore function to reinitialize the APLIC. Reviewed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-7-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add SiFive proprietary xsfceaseNick Hu1-0/+1
Using ISA string "xsfcease" to detect the support of the custom instruction "CEASE". Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-6-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: sbi: Add SiFive proprietary xsfcflushdloneNick Hu1-0/+1
Using ISA string "xsfcflushdlone" to detect the support of the SiFive L1D cache flush custom instruction. Reviewed-by: Cyan Yang <cyan.yang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Nick Hu <nick.hu@sifive.com> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-5-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils/cache: Add fdt cmo helpersNick Hu2-0/+115
Add the helpers to build up the cache hierarchy via FDT and provide some cmo functions for the user who want to flush the entire cache. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-4-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28utils: cache: Add SiFive ccache controllerVincent Chen3-0/+186
SiFive Composable cache is a L3 share cache of the core complex. Add this driver to support the share cache maintenance operations via the MMIO registers. Co-developed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-3-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add FDT cache libraryNick Hu4-0/+99
Add the FDT cache library so we can build up the cache topology via the 'next-level-cache' DT property. Co-developed-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Co-developed-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Andy Chiu <andy.chiu@sifive.com> Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-2-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-28lib: utils: Add cache flush libraryNick Hu4-0/+64
The current RISC-V CMO only defines how to flush a cache block. However, certain use cases, such as power management, may require flushing the entire cache. Therefore, a framework is being introduced to allow vendors to flush the entire cache using their own methods. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20251020-cache-upstream-v7-1-69a132447d8a@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-27lib: sbi: sbi_pmu: added checks for ctr_idx in matchAlexander Chuprunov1-4/+5
Previously, in sbi_pmu_ctr_cfg_match() function, ctr_idx was used immediately after pmu_ctr_find_fw() or pmu_ctr_find_hw() calls. In first case, array index was (ctr_idx - num_hw_ctrs), in second - ctr_idx. But pmu_ctr_find_fw() and pmu_ctr_find_hw() functions can return negative value, in which case writing in arrays with such indexes would corrupt sbi_pmu_hart_state structure. To avoid this situation, direct ctr_idx value check added. Signed-off-by: Alexander Chuprunov <alexander.chuprunov@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250918090706.2217603-4-alexander.chuprunov@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-27lib: sbi: sbi_pmu: fixed alignmentAlexander Chuprunov1-1/+1
Deleted spaces before brace in pmu_ctr_start_fw() for correct alignment. Signed-off-by: Alexander Chuprunov <alexander.chuprunov@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250918090706.2217603-3-alexander.chuprunov@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-27lib: sbi: sbi_pmu: fixed hw counters start for hartAlexander Chuprunov1-57/+70
Generally, hardware performance counters can only be started, stopped, or configured from machine-mode using mcountinhibit and mhpmeventX CSRs. Also, in opensbi only sbi_pmu_ctr_cfg_match() managed mhpmeventX. But in generic Linux driver, when perf starts, Linux calls both sbi_pmu_ctr_cfg_match() and sbi_pmu_ctr_start(), while after hart suspend only sbi_pmu_ctr_start() command called through SBI interface. This doesn't work properly in case when suspend state resets HPM registers. In order to keep counter integrity, sbi_pmu_ctr_start() modified. First, we're saving hw_counters_data, and after hart suspend this value is restored if event is currently active. Signed-off-by: Alexander Chuprunov <alexander.chuprunov@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250918090706.2217603-2-alexander.chuprunov@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: Allow custom CSRs in csr_read_num() and csr_write_num()Anup Patel1-53/+82
Some of the platforms use platform specific CSR access functions for configuring implementation specific CSRs (such as PMA registers). Extend the common csr_read_num() and csr_write_num() to allow custom CSRs so that platform specific CSR access functions are not needed. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20250930153216.89853-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-21lib: utils/timer: mtimer: Add SiFive CLINT v2 supportYong-Xuan Wang1-0/+1
The SiFive CLINT v2 is the HRT that supports the Zicntr extension. It is incompatible with the SiFive CLINT v0 due to differences in their control methods. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Co-developed-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250917105224.78291-1-yongxuan.wang@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-20platform: spacemit: Add HSM driverXianbin Zhu3-0/+147
Add code to bring up all 8 cores during OpenSBI initialization so that the Linux kernel can detect and use all cores properly. Co-authored-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Xianbin Zhu <xianbin.zhu@linux.spacemit.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250925-smt-k1-8-cores-v3-2-0885a8a70f8e@linux.spacemit.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-06lib: sbi: Prevent target domain same as the currentXiang W1-0/+4
Add error handling code to sbi_domain_context_enter to prevent the target domain from being the same as the current domain. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250903044619.394019-4-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-06lib: sbi: Add hart context init when first call enterXiang W1-14/+46
When entering sbi_domain_context_enter for the first time, the hart context may not be initialized. Add initialization code. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250903044619.394019-3-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-06lib: sbi: Add error handling to switch_to_next_domain_contextXiang W1-9/+12
Add error handling to switch_to_next_domain_context to ensure legal input. When switching contexts, ensure that the target to be switched is different from the current one. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250903044619.394019-2-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-10-06lib: serial: sifive-uart: add shared memory region for SiFive UARTYu-Chien Peter Lin1-1/+4
Add shared memory region so the driver has permission to access it in OpenSBI. Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250814111012.20151-1-peter.lin@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-30lib: utils/irqchip: fix aplic lock mechanism in xmsiaddrcfg(h)Yang Jialong1-7/+4
The section 4.5.4 "Supervisor MSI address configuration (smsiaddrcfg and smsiaddrcfgh)" of the AIA specification states that: "If register mmsiaddrcfgh of the domain has bit L set to one, then smsiaddrcfg and smsiaddrcfgh are locked as read-only alongside mmsiaddrcfg and mmsiaddrcfgh." In other words, the L bit is not defined for smsiaddrcfg[h] registers so fix aplic_writel_msicfg() accordingly. Signed-off-by: Yang Jialong <z_bajeer@yeah.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250806032924.3532975-1-z_bajeer@yeah.net Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: sbi_hsm: Use 64-bit CSR macro for menvcfgSamuel Holland1-16/+5
Simplify the code and remove preprocessor checks by treating menvcfg and menvcfgh together as one 64-bit value. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250908055646.2391370-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-09-16lib: sbi_hart: Do not call delegate_traps() in the resume flowSamuel Holland1-4/+4
The only purpose of this function is to program the initial values of mideleg and medeleg. However, both of these CSRs are now saved/restored across non-retentive suspend, so the values from this function are always overwritten by the restored values. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250908055646.2391370-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
generated by cgit v1.1 at 2025-12-29 05:45:00 +0000