aboutsummaryrefslogtreecommitdiff
path: root/include/sbi/sbi_misaligned_ldst.h
AgeCommit message (Collapse)AuthorFilesLines
2024-03-11include: sbi: rename sbi_misaligned_ldst.h to sbi_trap_ldst.hBo Gan1-23/+0
Signed-off-by: Bo Gan <ganboing@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org>
2020-03-28lib: sbi_misaligned_ldst: Remove mcause, scratch and hartid parametersAnup Patel1-9/+4
We remove mcause, scratch and hartid parameters from various functions for misaligned load/store handling because we can always get current HART id and current scratch pointer using just one CSR access. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
2019-12-16lib: Extend trap redirection for hypervisor v0.5 specAnup Patel1-0/+2
The hypervisor v0.5 spec introduces two new CSRs for both M-mode and HS-mode which need to be considered when redirecting traps hence this patch. Signed-off-by: Anup Patel <anup.patel@wdc.com>
2019-01-24all: Update copyright header in all filesAnup patel1-3/+3
This patch updates copyright header in all files as follows: 1. Makes "SPDX-License-Identifier: BSD-2-Clause" as first line 2. Change copyright year to 2019 for Western Digital Signed-off-by: Anup Patel <anup.patel@wdc.com>
2018-12-26lib: Add misaligned load/store trap handlingAnup Patel1-0/+26
We generally don't get misaligned load/store traps from Linux/U-Boot compiled using GCC 8.2 or higher but this is not true with older GCC toolchains. To tackle this we add misaligned load/store trap handling adopted from BBL sources but much more simpler. (Note: BBL sources can be found at https://github.com/riscv/riscv-pk.git) Signed-off-by: Anup Patel <anup.patel@wdc.com>