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Configure early PAU Global MMIO BAR registers to allow PAU MMIO
register accesses. This is done for each PAU. Enable the Powerbus
interface is mandatory for MMIO accesses.
For each OpenCAPI device, configure the bar registers to access to
the AFU MMIO and to the AFU Config Addr/Data registers.
AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K
(= 0x50000)
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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The PHB5 logic on P10 is pretty close to the P9's version. So
we keep our base phb4 implementation and just add the few changes
within if statements.
Signed-off-by: Jordan Niethe <jpn@ozlabs.au.ibm.com>
[clg: misc cleanups and fixes ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[Fixed compilation issue - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[Nick: Unify PHB4/PHB5 drivers ]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[Mikey: set default lane eq settings for phb5]
Signed-off-by: Michael Neuling <mikey@neuling.org>
[FB: squash commits + small cleanup ]
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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Adds a phys map for P10 based on the MMIO spreadsheet. Also updates
the phys map test to take a parameter which selects which map to test.
- Introduce new BAR for the PC subengine of XIVE2
On P10, the NVP (Process) and NVG (Group) pages share the MMIO range.
The even page gives access to the NVP structure and the odd page to
the NVG structure. OPAL only uses the NVP.
- Introduce new BARs for the VC subengine of XIVE2
On P10, the source ESB pages and END ESB pages have now their own MMIO range.
- Increase the MMIO range for the END ESB pages
The range was increased to 2TB to be able to address more END entries.
We now have a maximum of 16M entries per chip. The END and ESB ranges
are reordered for alignment.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[Folded Cedric's patches - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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This fixes multipchip rainier boot issue.
for Rainer:
chip0: ibm,primary-topology-index = < 0x0>;
chip1: ibm,primary-topology-index = < 0x4>;
chip2: ibm,primary-topology-index = < 0x8>;
chip3: ibm,primary-topology-index = < 0xc>;
for Denali:
node0:
chip0: ibm,primary-topology-index = < 0x0>;
chip1: ibm,primary-topology-index = < 0x1>;
chip2: ibm,primary-topology-index = < 0x2>;
chip3: ibm,primary-topology-index = < 0x3>;
node1:
chip0: ibm,primary-topology-index = < 0x4>;
chip1: ibm,primary-topology-index = < 0x5>;
chip2: ibm,primary-topology-index = < 0x6>;
chip3: ibm,primary-topology-index = < 0x7>;
Note that bmc_create_node() gets called very early in the boot process.
Hence we have to traverse through HDAT ntuple to get right topology index.
May be we can optimize pcid_to_topology_idx() function as its pretty
much duplicate of pcid_to_chip_id(). But for now lets keep it as
separate function.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
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SPDX makes it a simpler diff.
I have audited the commit history of each file to ensure that they are
exclusively authored by IBM and thus we have the right to relicense.
The motivation behind this is twofold:
1) We want to enable experiments with coreboot, which is GPLv2 licensed
2) An upcoming firmware component wants to incorporate code from skiboot
and code from the Linux kernel, which is GPLv2 licensed.
I have gone through the IBM internal way of gaining approval for this.
The following files are not exclusively authored by IBM, so are *not*
included in this update (I will be seeking approval from contributors):
core/direct-controls.c
core/flash.c
core/pcie-slot.c
external/common/arch_flash_unknown.c
external/common/rules.mk
external/gard/Makefile
external/gard/rules.mk
external/opal-prd/Makefile
external/pflash/Makefile
external/xscom-utils/Makefile
hdata/vpd.c
hw/dts.c
hw/ipmi/ipmi-watchdog.c
hw/phb4.c
include/cpu.h
include/phb4.h
include/platform.h
libflash/libffs.c
libstb/mbedtls/sha512.c
libstb/mbedtls/sha512.h
platforms/astbmc/barreleye.c
platforms/astbmc/garrison.c
platforms/astbmc/mihawk.c
platforms/astbmc/nicole.c
platforms/astbmc/p8dnu.c
platforms/astbmc/p8dtu.c
platforms/astbmc/p9dsu.c
platforms/astbmc/vesnin.c
platforms/rhesus/ec/config.h
platforms/rhesus/ec/gpio.h
platforms/rhesus/gpio.c
platforms/rhesus/rhesus.c
platforms/astbmc/talos.c
platforms/astbmc/romulus.c
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
[oliver: fixed up the drift]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Add the physical memory map for Axone systems. According to
'make hw-check', there are no holes or overlapping regions.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Acked-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Acked-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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When new chip types are added, phys_map_init() will need to know which
memory map it should use.
Instead of directly checking PVR, make it an argument to the function,
so that 'make hw-check' can test all the maps.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Acked-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Acked-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Use Software Package Data Exchange (SPDX) to indicate license for each
file that is unique to skiboot.
At the same time, ensure the (C) who and years are correct.
See https://spdx.org/
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
[oliver: Added a few missing files]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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Lowest Point of Coherency (LPC) memory allows the host to access memory on
an OpenCAPI device.
Define 2 OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE, for
assigning and clearing the memory BAR. (We try to avoid using the term
"LPC" to avoid confusion with Low Pin Count.)
At present, we use a fixed location in the address space, which means we
are restricted to a single range of 4TB, on a single OpenCAPI device per
chip. In future, we'll use some chip ID extension magic to give us more
space, and some sort of allocator to assign ranges to more than one device.
Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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There are three different ways we configure the MCD and memory map.
1) Old way (current way)
Skiboot configures the MCD and puts GPUs at 4TB and below
2) New way with MCD
Hostboot configures the MCD and skiboot puts GPU at 4TB and above
3) New way without MCD
No one configures the MCD and skiboot puts GPU at 4TB and below
The patch keeps option 1 and adds options 2 and 3.
The different configurations are detected using certain scoms (see
patch).
Option 1 will go away eventually as it's a configuration that can
cause xstops or data integrity problems. We are keeping it around to
support existing hostboot.
Option 2 supports only 4 GPUs and 512GB of memory per socket.
Option 3 supports 6 GPUs and 4TB of memory but may have some
performance impact.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This map is soon to be replaced, but we are going to keep it around
for a little while so that we support older hostboot firmware.
Rename it for now.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Removes the hard coded address and the useless warning
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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Currently we pass in a proc_chip structure to phys_map_get(). All we we
really need from this structure is the Global Chip ID (GCID). This
patch reworks the function so that we only need to pass the GCID which
allows us to use it before the proc_chip structures have been
initialised (i.e in the HDAT parser).
Cc: Michael Neuling <mikey@neuling.org>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Acked-By: Michael Neuling <mikey@neuling.org>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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We don't use this region currrently but we should add for
completeness.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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This adds a global map for allocating physical memory address. This
centralises physical memory space allocations into one location rather
than spread through, PHB, XIVE, NX etc.
This adds a new call phys_map_get() which takes a chip, type and index
and returns a address and size for the region to be used.
An error in a call to this function crashes skiboot. This is done
since bogus calls here are going to be hit by developers not users and
they need to be fixed.
Currently only P9 is implemented but other chips should be easy to
add. On P9 BARs are generally set by skiboot. On P8 this was done by
hostboot so this is not needed there.
This just adds the infrastructure. User (PHB4, XIVE etc) will be
migrated in subsequent patches.
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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