diff options
| author | Alistair Popple <alistair@popple.id.au> | 2021-08-04 12:50:59 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-08-06 12:22:50 +0530 |
| commit | 048ead0d436797b7c6eadce16531b84e7437ad2a (patch) | |
| tree | 233620c8ce9aa6c9dbc359031b7a8079fa7af6a3 /include/phys-map.h | |
| parent | 02f90c12a7949c34a2d405f939bef1f352a542d4 (diff) | |
| download | skiboot-048ead0d436797b7c6eadce16531b84e7437ad2a.zip skiboot-048ead0d436797b7c6eadce16531b84e7437ad2a.tar.gz skiboot-048ead0d436797b7c6eadce16531b84e7437ad2a.tar.bz2 | |
hw/phys-map/p10: Add P10 MMIO map
Adds a phys map for P10 based on the MMIO spreadsheet. Also updates
the phys map test to take a parameter which selects which map to test.
- Introduce new BAR for the PC subengine of XIVE2
On P10, the NVP (Process) and NVG (Group) pages share the MMIO range.
The even page gives access to the NVP structure and the odd page to
the NVG structure. OPAL only uses the NVP.
- Introduce new BARs for the VC subengine of XIVE2
On P10, the source ESB pages and END ESB pages have now their own MMIO range.
- Increase the MMIO range for the END ESB pages
The range was increased to 2TB to be able to address more END entries.
We now have a maximum of 16M entries per chip. The END and ESB ranges
are reordered for alignment.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[Folded Cedric's patches - Vasant]
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Diffstat (limited to 'include/phys-map.h')
| -rw-r--r-- | include/phys-map.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/phys-map.h b/include/phys-map.h index 97351a7..a3394c0 100644 --- a/include/phys-map.h +++ b/include/phys-map.h @@ -42,7 +42,11 @@ enum phys_map_type { MC_OCMB_CFG, MC_OCMB_MMIO, XSCOM, - RESV + RESV, + XIVE_NVC, + XIVE_NVPG, + XIVE_ESB, + XIVE_END, }; extern void phys_map_get(uint64_t gcid, enum phys_map_type type, |