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2023-11-27hw/imc: Detect BML and fix core countersRyan Grimm1-0/+1
On systems running BML we started noticing this in the skiboot log: [ 409.088819302,3] XSCOM: write error gcid=0x0 pcb_addr=0x20000060 stat=0x4 [ 409.088823446,3] ELOG: Error getting buffer to log error [ 409.088824806,3] XSCOM: Write failed, ret = -26 [ 409.088825797,3] IMC: error in xscom_write for pdbar [ 0.468976][ T19] core_imc memory allocation for cpu 0 failed [ 0.468993][ T1] IMC PMU core_imc Register failed I tracked down that bad pcb_addr to this line in the code: pdbar_addr = get_imc_scom_addr_for_quad(phys_core_id, pdbar_scom_index[port_id]); I found that pdbar_scom_index was not initialized because, like mambo, we don't have the IMC catalog in memory. So, in imc_init we error out and never initialize it in setup_imc_scoms. This patch adds a chip quirk QUIRK_BML because it seems like a reasonable thing to do and it's easy to put a BML {}; in the device tree like Mambo, Awan, etc. It is tested on a Rainier and errors are gone and /sys/devices/core_imc shows up as expected. Signed-off-by: Ryan Grimm <grimm@linux.ibm.com> Reviewed-By: Madhavan Srinivasan <maddy@linux.ibm.com>
2023-10-11hdata: Remove legacy SPIRA structureNicholas Piggin1-11/+9
skiboot only supports POWER8 > DD1 now, all supported platforms should use the new SPIRA-S/H structure. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-15core/device: Add function to return child node using name at substring "@"Athira Rajeev1-0/+3
Add a function dt_find_by_name_before_addr() that returns the child node if it matches till first occurrence at "@" of a given name, otherwise NULL. This is helpful for cases with node name like: "name@addr". In scenarios where nodes are added with "name@addr" format and if the value of "addr" is not known, that node can't be matched with node name or addr. Hence matching with substring as node name will return the expected result. Patch adds dt_find_by_name_before_addr() function and testcase for the same in core/test/run-device.c Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Reviewed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> [arbab: Refactor the loop to fix possible memory leak] Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Register OPAL_IPMI_SEND/RECV calls backChristophe Lombard1-0/+5
backend apis to support partially: OPAL_IPMI_SEND: send an IPMI message to the service processor OPAL_IPMI_RECV: read an ipmi message of type ``ipmi_msg`` from ipmi message queue ``msgq`` into host OS structure ``opal_ipmi_msg`` Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Register OPAL_RTC_READ/WRITE calls backChristophe Lombard1-0/+5
OPAL_RTC_READ/WRITE are used to retrieve and write the time. PLDM stack provides GetBiosDateTimeReq and SetBiosDateTimeReq commands to exercise. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Update boot progress stateChristophe Lombard1-0/+12
PLDM Event Messages are PLDM monitoring and control messages that are used by a PLDM terminus to synchronously or asynchronously report PLDM events to a central party called the PLDM Event Receiver. This patch allows to send a: - generic sensor events (events related to PLDM numeric and state sensors). - boot progress sensor event. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Handle Watchdog timer.Christophe Lombard1-0/+5
Encode a PLDM platform event message to send the heartbeat to the BMC. Watchdog is "armed" when a PLDM_EVENT_MESSAGE_GLOBAL_ENABLE_ASYNC_KEEP_ALIVE is received. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Register PLDM as a blocklevel deviceChristophe Lombard1-0/+5
In the same way that ipmi-hiomap implements the PNOR access control protocol, this patch allows to "virtualize" the content of a BMC flash based on lid files. Previously, flash PNOR partitions were viewed this way: partitionXX=NAME, start address, end address, flags The content of each partition is now stored in a lid file. In order to continue to use the libflash library, we manually fill in the contents of a fake flash header when accessing offset 0. This reproduces the behavior via ipmi-hiomap of reading the flash header on the BMC. For the reading and writing of BMC lids files, we convert the virtual addresses of these 'fake' partitions by identifying: lid id. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Lid ids string parsingChristophe Lombard1-0/+7
This patch parses the "hb_lid_ids" string from bios tables and complete the global list of lid files. Each entry in the list contains the name, the id, the length of the lid file and the virtual address start access. This virtual address is used for for PNOR Resource Provider operations. 16 MB of VMM address are reserved space per section. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Update "bmc-firmware-version" device-tree fieldChristophe Lombard1-0/+5
Use the GetFruRecordByOptionReq command to retrieve the bmc information with: "FRU Field Type": Version "FRU Record Set Identifier": 1, "FRU Record Type": "General(1)" and update the "bmc-firmware-version" device-tree field. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Send a system chassis Off-Soft Graceful requestChristophe Lombard1-0/+5
Set the state information of the PLDM effecter identified by: the entity type (PLDM_ENTITY_SYSTEM_CHASSIS) and the state set PLDM_STATE_SET_SYSTEM_POWER_STATE with the effecter state: PLDM_STATE_SET_SYS_POWER_STATE_OFF_SOFT_GRACEFUL to request a platform off. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Send a system firmware Graceful Restart requestChristophe Lombard1-0/+5
Set the state information of the PLDM effecter identified by: the entity type (PLDM_ENTITY_SYS_FIRMWARE) and the state set PLDM_STATE_SET_SW_TERMINATION_STATUS with the effecter state: PLDM_SW_TERM_GRACEFUL_RESTART_REQUESTED to request a platform restart. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: Encode GetTID responseChristophe Lombard1-0/+8
A PLDM Terminus is defined as the point of communication termination for PLDM messages and the PLDM functions associated with those messages. Given a PLDM terminus, a mechanism is required that can uniquely identify each terminus so that the semantic information can be bound to that identification. The Terminus ID (TID) is a value that identifies a PLDM terminus. TIDs are used in PLDM messages when it is necessary to identify the PLDM terminus that is the source of the PLDM Message. The GetTID command is used to retrieve the present Terminus ID (TID) setting for a PLDM Terminus. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12core/pldm: PLDM over MCTP BindingChristophe Lombard1-0/+24
Enable the mctp binding over LPC bus interface and new wrappers to send and receive PLDM messages over the mctp library. PLDM is supported as a message type over MCTP. PLDM over MCTP binding defines the format of PLDM over MCTP messages. An MCTP Endpoint is the terminus for MCTP communication. A physical device that supports MCTP may provide one or more MCTP Endpoints. Endpoints are addressed using a logical address called the Endpoint ID, or EID. EIDs in MCTP are analogous to IP Addresses in Internet Protocol networking. The BMC EID default is 8. First byte of the PLDM over MCTP Message Fields identifies the MCTP message as carrying a PLDM message: Message Type (7 bits) PLDM = 0x01 (000_0001b). Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12hw/ast-bmc: Initialize ast lpc mctp bindingChristophe Lombard1-0/+20
The Management Component Transport Protocol (MCTP) defines a communication model intended to facilitate communication. This patch initialize MCTP binding over LPC Bus interface. Several steps must be performed: - Initialize the MCTP core (mctp_init()). - Initialize a hardware binding as AST LPC mode host (mctp_astlpc_init()). - Register the hardware binding with the core (mctp_register_bus()), using a predefined EID (Host default is 9). To transmit a MCTP message, mctp_message_tx() is used. To receive a MCTP message, a callback need to be provided and registered through mctp_set_rx_all(). For the transfer of MCTP messages, two basics components are used: - A window of the LPC FW address space, where reads and writes are forwarded to BMC memory. - An interrupt mechanism using the KCS interface. hw/ast-bmc/ast-mctp.c is compilated if the compiler flag CONFIG_PLDM is set. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12hw: Move lpc firmware space helpersChristophe Lombard1-0/+6
Add new lpc helpers for doing a bulk io to firmware space. Reviewed-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12pldm: Export logging featureChristophe Lombard1-0/+1
To retrieve specific log traces from the external library: libmctp, we need to export the logging api. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12include/asm: Create asm_byteorder.h header fileChristophe Lombard1-0/+10
This file is used by the external library: libpldm. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12include: Provide endian conversion functionsChristophe Lombard1-0/+24
Implement the BSD endian conversion functions in terms of the ccan ones since the external libraries: libpldm and libmctp use them heavily. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-09-12include: Expand print conversion specificier macrosChristophe Lombard1-0/+6
Add PRIxu macros into include inttypes file. These macros are required by the external library: libmctp. Signed-off-by: Christophe Lombard <clombard@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-08-09pci: Remove MVE opal callsJoel Stanley1-6/+0
These callbacks were used by the p7ioc code that was removed a long time ago. Add them to the list of removed calls and delete the dead code. Linux has removed the code that called these functions in v6.5-rc1. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06ipmi: remove unused OS watchdog supportNicholas Piggin1-3/+0
This code hasn't been enabled, remove it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06ipmi: flush the ipmi message queue before booting a kernelNicholas Piggin1-1/+6
Bring ipmi to a consistent state before booting a kernel by flushing all outstanding messages. The OS may not start kicking the IPMI state machine for some time. For example, without this change, when booting in QEMU, the IPMI command issued by ipmi_wdt_final_reset() to disable the watchdog is not sent to the BMC before the OS boots, effectively leaving the watchdog enabled until the OS begins to drive OPAL pollers. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-06-06mem_region: Add a local_free functionNicholas Piggin1-0/+4
This allows memory to be allocated with local_alloc() to be freed. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2023-02-27hw/phb4: Use symbols when accessing PEC registersFrederic Barrat1-0/+1
This patch improves readability just a tiny bit by using symbols, most of them already existing, instead of values when accessing the PEC registers. No functional changes. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-07-05interrupts: Speed up opal interrupts scanningFrederic Barrat1-0/+1
When looking for which interrupts are serviced by opal, we scan all sources and query every single interrupt to know if it's for linux or opal. An optimization was made so that if the source doesn't have an 'interrupt' op (=the handler) or an 'attributes' op (to do the query), then we can skip the source. That's all good. However, when xive was introduced, the 'irq_source' defining those ops was wrapped in a 'xive_src' source which adds a level of indirection for those 'attributes' and 'interrupt' ops. So the previous optimization no longer works: the 'attributes' and 'interrupt' ops are defined from the wrapper, but if we could look past the indirection, we would realize they are not. That is getting problematic for the rather large generic IPIs source. We have 8 million such interrupts defined per chip on P10 and because the above optimization is no longer kicking in, we are now querying every single one of them to know if it is for opal. Real hardware swallows it without much difficulty, but simulators don't. Running qemu on my laptop, the full scan takes ~12 seconds per chip! This patch adds a callback for an interrupt source to report whether it has opal interrupts. If the source doesn't define it, then we fallback to looking at the 'interrupt' and 'attributes' ops, like before, as it is still useful on P8. We can then define that new callback on the xive sources, allowing to look past the indirection level and skip scanning the source when appropriate. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-06-13cpu: Fix HID SPR icache flushing and attn change sequenceNicholas Piggin1-2/+4
Changing the HID attn enable bit on POWER9 and POWER10 requires the icache to be flushed *after* ATTN is changed. It is not clear that it may be done at the same time, so move it to after the attn bit change. Flushing the icache with HID requires a 0->1 edge and the bit does not reset back to 0, so first write 1 then 0 ready for the next flush. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-06-13core: detect LPAR-per-core mode and report in dtNicholas Piggin1-0/+2
Some firmware configurations boot in LPAR-per-core mode, which is not compatible with KVM on POWER9 and later machines. Detect which LPAR mode the boot core is in (all others will be set the same way), and if booted in LPAR-per-core mode then print a warning and add a device-tree entry that the OS can test for. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2022-02-04Fix array-bound compilation warningsAbhishek Singh Tomar1-0/+12
Resolves : the warray bounds warning during compilation /build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds] 34 | #define memset __builtin_memset hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset' 1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE); use volatile pointer to avoid optimization introduced with gcc-11 on constant address assignment to pointer. Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8Stewart Smith1-0/+7
Make the P8 NPU code depend on CONFIG_P8. This requires converting a low level function to a no-op because the HMI NPU handling is not so cleanly layered. This saves an extra 6kb of skiboot.lid.xz. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hw/slw: split P8 specific code into its own fileNicholas Piggin2-12/+48
POWER8 support is large and significantly different than P9/10 code. This change prepares to make P8 support configurable. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Removed commented headers in slw.c ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03SBE: create processor-independent timer APIsNicholas Piggin3-6/+19
Rather than have code call processor-specific SBE routines depending on version, hide those details in SBE APIs. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [ clg: Fixed run-timer test ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03hwprobe: convert PHB, NPU, PAU subsystems to hwprobeStewart Smith1-5/+0
Reviewed-by: Dan Horák <dan@danny.cz> [npiggin: split out from initial hwprobe pach] Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-03Introduce hwprobe facility to avoid hard-coding probe functionsStewart Smith1-1/+38
hwprobe is a little system to have different hardware probing modules run in the dependency order they choose rather than hard coding that order in core/init.c. Reviewed-by: Dan Horák <dan@danny.cz> Signed-off-by: Stewart Smith <stewart@flamingspork.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-23core/cpu: make cpu idle states simplerNicholas Piggin1-2/+3
Rework the CPU idle state code: * in_idle is true for any kind of idle including spinning. This is not used anywhere except for state assertions for now. * in_sleep is true for idle that requires an IPI to wake up. * in_job_sleep is true for in_sleep idle which is also cpu_wake_on_job. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-26opal-api: Drop diagnostics data type symbol for PHB5Frederic Barrat1-1/+0
All PHB5 error registers read when getting the PHB diagnostics data have the exact same definitions as on PHB4, so we don't need any new type. OPAL_PHB_ERROR_DATA_TYPE_PHB5 is not used in skiboot. It's never been imported on linux, so it is safe to remove the symbol. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: Add support for OpenCAPI Persistent Memory devices.Christophe Lombard3-0/+15
Lowest Point of Coherency (LPC) memory allows the host to access memory on an OpenCAPI device. When the P10 chip accesses memory addresses on the AFU, the Real Address on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR defines the range of Real Addresses that represent AFU memory. The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE are used to manage the AFU momory. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: mmio invalidatesChristophe Lombard2-0/+10
The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is not used due to performance problems caused by the mismatch between the ERAT and Bloom Filter sizes. When the Address Translation Mode requires TLB and SLB Invalidate operations to be initiated using MMIO registers, a set of registers like the following is used: • XTS MMIO ATSD0 LPARID register • XTS MMIO ATSD0 AVA register • XTS MMIO ATSD0 launch register, write access initiates a shoot down • XTS MMIO ATSD0 status register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: update current opal call functionsChristophe Lombard2-0/+20
Update the content of three current OPAL API calls to support PAU. - OPAL_NPU_SPA_SETUP The Shared Process Area (SPA) is a table containing one entry (a "Process Element") per memory context which can be accessed by the OpenCAPI device. - OPAL_NPU_SPA_CLEAR_CACHE The PAU keeps a cache of recently accessed memory contexts. When a Process Element is removed from the SPA, the cache for the link must be cleared. - OPAL_NPU_TL_SET The Transaction Layer specification defines several templates for messages to be exchanged on the link. During link setup, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: link trainingChristophe Lombard3-0/+53
Add elementary functions to handle a phb complete, fundamental and hot resets. For the time being, specific creset and hreset are not supported. A complete fundamental reset is based on the following steps, in this order: - Place all bricks into Fence state - Disable BARs - Reset ODL to Power-on Values - Set the i2c reset pin in output mode - Initialize PHY Lanes - Deassert ODL reset - Clear the the i2c reset pin - Unfence bricks - Enable BARs - Enable ODL training mode Link training is also set up. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: phy initChristophe Lombard1-0/+11
Follow the Procedure IO_INIT_RESET_PON as described in the P10 OPHY workbook document to reset and initialize the PHY lanes. The memory mapped SRAM (64 bit aligned) has to be used to configure the PHY, which is reachable the linked registers: address and data. The different links can be configured at the same time, that implies using a global lock to avoid conflicts. Authored-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: hmi scom dumpChristophe Lombard5-1/+35
This patch add a new function to dump PAU registers when a HMI has been raised and an OpenCAPI link has been hit by an error. For each register, the scom address and the register value are printed. The hmi.c has been redesigned in order to support the new PHB/PCIEX type (PAU OpenCapi). Now, the *npu* functions support NPU and PAU units of P8, P9 and P10 chips. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: complete phb opsChristophe Lombard1-0/+9
Add more PHB interfaces: - to control pci error type in case of freeze. - add the addresses of the registers needed by the OS to handle translation failures. - to detect the fence state of a specific brick - to configure BDF (Bus Device Function) and PE (Partitionable Endpoint) for context identification. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: enable interrupt on errorChristophe Lombard2-0/+14
The default action for the errors (unexpected errors on the opencapi link) reported in the PAU FIR2 registe is mostly set to system checkstop. This patch changes the default action of those errors so that the PAU will raise an interrupt instead. Interrupt information are logged so that the error can be debugged and linux can catch the event. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: translation layer configurationChristophe Lombard2-0/+39
Next main part of the hypervisor PAU initialization. The P10 PAU supports two OpenCAPI links. The PAU provides various configuration selections for both of the OCAPI Link Transaction Layer functions (OTLs). These include a link enable, behavior controls, debug modes, and virtual channel credits to send to the AFU. The OTL Configuration 0, OTL Configuration 1, OTL Configuration 2, and TLX Credit Configuration registers are used to control these functions. This patch completes the PAU configuration following the sections 17.1.3.4 to 17.1.3.10.2 of the workbook document. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: enabling opencapiChristophe Lombard2-0/+44
Enable OpenCAPI mode for each brick which are connected to be used in this mode. This is be done through 7 steps as described in the P10 OCAPI 5.0 Processing Unit Workbook document, section: 17.1.3.1 Enabling OpenCAPI. The following sequences must be performed: 1. Set Transport MUX controls to select OpenCAPI 2. Enable Clocks in XSL 3. Enable Clocks in MISC 4. Set NPCQ configuration 5. Enable XSL-XTS Interfaces 6. Enable State-machine allocation Enabling the NTL/GENID BARS allows to access to the MMIO registers. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: create phbChristophe Lombard3-0/+22
Implement the necessary operations for the OpenCAPI PHB type and inform the device-tree properties associated. The OpenCapi PCI config Addr/Data registers are reachable through the Generation-ID Registers MMIO BARS. The Config Address and Data registers are located at the following offsets from the AFU Config BAR plus 320 KB. • Config Address for Brick 0 – Offset 0 • Config Data for Brick 0 – Offsets: ◦ 128 – 4-byte config register • Config Address for Brick 1 – Offset 256 • Config Data for Brick 1 – Offsets: ◦ 384 – 4-byte config register Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: assign barsChristophe Lombard3-0/+109
Configure early PAU Global MMIO BAR registers to allow PAU MMIO register accesses. This is done for each PAU. Enable the Powerbus interface is mandatory for MMIO accesses. For each OpenCAPI device, configure the bar registers to access to the AFU MMIO and to the AFU Config Addr/Data registers. AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K (= 0x50000) Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19rainier: detect pau devicesChristophe Lombard2-0/+8
Update the platform_ocapi structure to store Rainier platform-specific values for detecting and resetting OpenCAPI devices via the module I2C (PCA9553) The unique number I2C bus ID associated to each OpenCapi device is get from the I2C port and engine. (De)Assert a reset and detect an OpenCapi device is available through the I2C bus id and address. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
2021-10-19pau: introduce supportChristophe Lombard4-0/+129
OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable PHYs, Datalink Layer Logic and Transaction Layer Logic to be included. The PHYs are the physical connection to the OCAPI interconnect. The Datalink Layer provides link training. The Transaction Layer executes the cache coherent and data movement commands on the P10 chip. The PAU provides the Transaction Layer functionality for the OCAPI link(s) on the P10 chip. The P10 PAU supports two OCAPI links. Six accelerator units PAUs are instantiated on the P10 chip for a total of twelve OCAPI links. This patch adds PAU opencapi structure for supporting OpenCapi5. hw/pau.c file contains main of PAU management functions. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
generated by cgit v1.1 at 2024-06-29 01:38:49 +0000