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path: root/hw/npu2.c
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2017-09-12npu2: Add vendor cap for IRQ testingSam Bobroff1-0/+28
2017-09-12npu2: Enable recoverable data link (no-stall) interruptsSam Bobroff1-15/+121
2017-09-12npu2: Update NPU to NPU2 in comments and messagesSam Bobroff1-13/+13
2017-09-12npu2: Implement FLRReza Arbab1-1/+28
2017-09-12npu2: Add npu2_clear_link_flag()Reza Arbab1-0/+7
2017-08-30hw/npu2.c: Add ibm, nvlink-speed device-tree propertyAlistair Popple1-0/+8
2017-08-22NPU2: fix missing unlockStewart Smith1-1/+1
2017-08-04hw/npu2.c: Add temporary scominits to enable NVLink mode on DD2Alistair Popple1-0/+36
2017-08-04npu2: Allow POWER9 DD2 in ec level checkReza Arbab1-1/+1
2017-08-04npu2: Set the XTS config2 registerReza Arbab1-0/+5
2017-08-04npu2: Adjust content of the NTL BARReza Arbab1-3/+10
2017-08-04npu2: Adjust content of the GENID BARReza Arbab1-2/+2
2017-08-04npu2: Add NPU2_GPU1_MEM_BARReza Arbab1-14/+16
2017-08-04npu2: Use read-modify-write in npu2_assign_gmb()Reza Arbab1-3/+5
2017-08-04npu2: Rename variable in npu2_assign_gmb()Reza Arbab1-14/+14
2017-08-04npu2: Fix NPU/PHY0/PHY1 stack orderReza Arbab1-7/+11
2017-08-04npu2: Fix indirect SCOM addressesReza Arbab1-3/+11
2017-08-04npu2: Add a function to detect POWER9 DD1Reza Arbab1-0/+10
2017-08-01hw/npu2: fix typo in commentStewart Smith1-1/+1
2017-07-13numa/associativity: Add a new level of NUMA for GPU'sBalbir Singh1-1/+2
2017-06-30npu2: Use phys-map to get MMIO BARsAndrew Donnellan1-50/+46
2017-06-21hw/npu2.c: Fix device aperture calculationAlistair Popple1-2/+4
2017-06-20hw/npu2.c: Change MCD BAR allocation orderAlistair Popple1-2/+7
2017-06-20NPU2: Add flag to nvlink config space indicating DL reset stateAlistair Popple1-2/+9
2017-06-20hw/npu2.c: Hardcode MSR_SF when setting up npu XTS contextsAlistair Popple1-2/+4
2017-06-20hw/npu2-hw-procedures.c: Add nvram option to override zcal calculationsAlistair Popple1-0/+9
2017-06-16hw/phys_map: Use GCIDs as a chip indexOliver O'Halloran1-5/+5
2017-06-06npu2: Fix npu2_{read,write}_4b()Reza Arbab1-4/+6
2017-06-06hw/npu2.c: Fix opal_npu_map_lpar to search for existing BDFAlistair Popple1-2/+2
2017-06-06hw/npu2.c: Add memory coherence directory programmingAlistair Popple1-1/+38
2017-06-06hw/npu2.c: Use phys-map to get GPU memory BARsAlistair Popple1-76/+26
2017-05-10npu2: Do not attempt to initialise non DD1 hardwareAlistair Popple1-0/+7
2017-05-10npu2: Fix BAR mapping for multiple chipsAlistair Popple1-97/+135
2017-05-10npu2: Fix argument order to npu2_scom_write in BAR setupAlistair Popple1-1/+1
2017-05-03npu, npu2: Describe diag data size in device treeRussell Currey1-0/+1
2017-03-30npu2: Add hardware link training proceduresAlistair Popple1-2/+9
2017-03-30npu2: Add OPAL calls for nvlink2 address translation servicesAlistair Popple1-1/+229
2017-03-30npu2: Allocate GPU memory and describe it in the dtReza Arbab1-0/+196
2017-03-30Introduce NPU2 supportAlistair Popple1-0/+1388