diff options
| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-07-31 21:37:02 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-04 17:13:10 +1000 |
| commit | ec99176c1cfc75a2b7e712ab817f00cd8ef18c86 (patch) | |
| tree | 69bdaebc4c1a334058337fb37a8ab48fe51b2ece /hw/npu2.c | |
| parent | ec27983716d1c9fd72657dc4c74659eded7598ac (diff) | |
| download | skiboot-ec99176c1cfc75a2b7e712ab817f00cd8ef18c86.zip skiboot-ec99176c1cfc75a2b7e712ab817f00cd8ef18c86.tar.gz skiboot-ec99176c1cfc75a2b7e712ab817f00cd8ef18c86.tar.bz2 | |
npu2: Add NPU2_GPU1_MEM_BAR
POWER9 DD2 has added a second GPU memory BAR. Use it, but continue to
program things the old way on DD1 systems.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Cc: Alistair Popple <alistair@popple.id.au>
Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
Diffstat (limited to 'hw/npu2.c')
| -rw-r--r-- | hw/npu2.c | 30 |
1 files changed, 16 insertions, 14 deletions
@@ -581,7 +581,7 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) struct npu2 *p = ndev->npu; int peers, mode; uint32_t bdfn; - uint64_t base, size, reg, val, old_val; + uint64_t base, size, reg, val, old_val, gmb; /* Need to work out number of link peers. This amount to * working out the maximum function number. So work start at @@ -631,28 +631,30 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) mode += ndev->bdfn & 0x7; val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode); + gmb = NPU2_GPU0_MEM_BAR; + if (NPU2DEV_BRICK(ndev) && !is_p9dd1()) + gmb = NPU2_GPU1_MEM_BAR; + reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_0, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_0, gmb); - old_val = npu2_read(p, reg); - if (NPU2DEV_BRICK(ndev)) - val = SETFIELD(PPC_BITMASK(32, 63), old_val, val >> 32); - else - val = SETFIELD(PPC_BITMASK(0, 31), old_val, val >> 32); + if (is_p9dd1()) { + old_val = npu2_read(p, reg); + if (NPU2DEV_BRICK(ndev)) + val = SETFIELD(PPC_BITMASK(32, 63), old_val, val >> 32); + else + val = SETFIELD(PPC_BITMASK(0, 31), old_val, val >> 32); + } npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_1, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_1, gmb); npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_2, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_2, gmb); npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), - NPU2_BLOCK_SM_3, - NPU2_GPU0_MEM_BAR); + NPU2_BLOCK_SM_3, gmb); npu2_write(p, reg, val); return 0; |