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2017-08-11HDAT: Add chip-id property to ipmi sensorsVasant Hegde1-0/+36
Presently we do not have a way to map sensor to chip id. Hence we are always passing chip id 0 for occ_reset request (see occ_sensor_id_to_chip()). This patch adds chip-id property to sensors (whenever its available) so that we can map occ sensor to chip-id and pass valid chip-id to occ_reset request. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Enhanced PCIe training tracingMichael Neuling2-2/+63
This add more details to the PCI training tracing (aka Rick Mata mode). It enables the PCIe Link Training and Status State Machine (LTSSM) tracing and details on speed and link width. Output now looks like this when enabled (via nvram): [ 1.096995141,3] PHB#0000[0:0]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.102849137,3] PHB#0000[0:0]: TRACE:0x0000102101000000 11ms presence GEN1:x16:polling [ 1.104341838,3] PHB#0000[0:0]: TRACE:0x0000182101000000 14ms training GEN1:x16:polling [ 1.104357444,3] PHB#0000[0:0]: TRACE:0x00001c5101000000 14ms training GEN1:x16:recovery [ 1.104580394,3] PHB#0000[0:0]: TRACE:0x00001c5103000000 14ms training GEN3:x16:recovery [ 1.123259359,3] PHB#0000[0:0]: TRACE:0x00001c5104000000 51ms training GEN4:x16:recovery [ 1.141737656,3] PHB#0000[0:0]: TRACE:0x0000144104000000 87ms presence GEN4:x16:L0 [ 1.141752318,3] PHB#0000[0:0]: TRACE:0x0000154904000000 87ms trained GEN4:x16:L0 [ 1.141757964,3] PHB#0000[0:0]: TRACE: Link trained. [ 1.096834019,3] PHB#0001[0:1]: TRACE:0x0000001101000000 0ms GEN1:x16:detect [ 1.105578525,3] PHB#0001[0:1]: TRACE:0x0000102101000000 17ms presence GEN1:x16:polling [ 1.112763075,3] PHB#0001[0:1]: TRACE:0x0000183101000000 31ms training GEN1:x16:config [ 1.112778956,3] PHB#0001[0:1]: TRACE:0x00001c5081000000 31ms training GEN1:x08:recovery [ 1.113002083,3] PHB#0001[0:1]: TRACE:0x00001c5083000000 31ms training GEN3:x08:recovery [ 1.114833873,3] PHB#0001[0:1]: TRACE:0x0000144083000000 35ms presence GEN3:x08:L0 [ 1.114848832,3] PHB#0001[0:1]: TRACE:0x0000154883000000 35ms trained GEN3:x08:L0 [ 1.114854650,3] PHB#0001[0:1]: TRACE: Link trained. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11hdat: Fix PCIe GEN4 lane-eq setting for DD2Michael Neuling1-4/+19
For PCIe GEN4, DD2 uses only 1 byte per PCIe lane for the lane-eq settings (DD1 uses 2 bytes). This fixes the HDAT parsing to cope with this. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11hdat: Add POWER9 DD2.0 specific pa_featuresMichael Neuling1-1/+20
Same as the default but with TM off. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11hdat: Make is_power9n() globalMichael Neuling2-12/+16
This splits out is_power9n() so it can be used elsewhere. It also adds a check for for POWER9 so the function does more of what it's name suggests (and so the caller doesn't need to do it). Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Fix reading wrong size registers in EEH dumpRussell Currey1-3/+3
These registers are supposed to be 16bit, and it makes part of the register dump misleading. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Ignore slot state if performing complete resetRussell Currey1-1/+4
If a PHB is being completely reset, its state is about to be blown away anyway, so if it's not in an appropriate state, creset it regardless. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Prepare for link down when creset called from kernelRussell Currey1-0/+1
phb4_creset() is typically called by functions that prepare the link to go down. In cases where creset() is called directly by the kernel, this isn't the case and it can cause issues. Prepare for link down in creset, just like we do in freset and hreset. Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Skip attempting to fix PHBs broken on bootRussell Currey1-0/+4
If a PHB is marked broken it didn't work on boot, and if it didn't work on boot then there's no point trying to recover it later Signed-off-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11phb4: Fix duplicate in EEH register dumpRussell Currey1-1/+0
Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11xive: Check for valid PIR index when decodingRussell Currey1-0/+4
This fixes an unlikely but possible assert() fail on kdump. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell Currey <ruscur@russell.cc> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11Recognize the 2s2u zz platformAnanth N Mavinakayanahalli1-0/+1
OPAL currently doesn't know about the 2s2u zz. It recognizes such a box as a generic BMC machine and fails to boot. Add the 2s2u as a supported platform. There will subsequently be a 2s2u-L system which may have a different compatible property, which will need to be handled later. Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-11hdata_to_dt: use a realistic PVR and chip revisionStewart Smith3-42/+53
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-10hdata/spira: POWER9 NX isn't software compatible with P7/P8 NX, don't claim soStewart Smith2-11/+21
Fixes: 2512953c7c6dc3b479d159d9bce8206219951164 Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04hw/npu2.c: Add temporary scominits to enable NVLink mode on DD2Alistair Popple1-0/+36
DD2 requires NVLink mode to be specifically enabled per brick. A longer term solution is currently being worked on but in the mean time we can safely work around it by manually doing the scominit here. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04xscom: Add xscom_write_mask() functionAlistair Popple2-1/+16
It is common for xscom registers to only contain specific bit fields that need to be modified without altering the rest of the register. This adds a convenience function to perform xscom read-modify-write operations under a mask. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Allow POWER9 DD2 in ec level checkReza Arbab1-1/+1
Don't bail when we encounter a POWER9 DD2.x chip. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-By: Alistair Popple <alistair@popple.id.au> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Set the XTS config2 registerReza Arbab2-0/+6
POWER9 DD2 has added a new bit we'd like to set: "XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the flush" This has passed sanity tests with 4.12 kernels, which are capable of exercising this capability. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Adjust content of the NTL BARReza Arbab2-5/+14
Reflect the changed NTL BAR layout in POWER9 DD2. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Adjust content of the GENID BARReza Arbab2-4/+5
Reflect the changed GENID BAR layout in POWER9 DD2. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Add NPU2_GPU1_MEM_BARReza Arbab2-14/+17
POWER9 DD2 has added a second GPU memory BAR. Use it, but continue to program things the old way on DD1 systems. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alistair Popple <alistair@popple.id.au> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Use read-modify-write in npu2_assign_gmb()Reza Arbab1-3/+5
We currently set each half of the GPU memory BAR by OR'ing our half into what is already there. This allows a possible conflict if Hostboot or other system boot software has already written to the BAR. Set each half of the BAR value directly instead of using OR. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Cc: Alistair Popple <alistair@popple.id.au> Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Rename variable in npu2_assign_gmb()Reza Arbab1-14/+14
Rename 'gmb' to 'val'. No functional change. This is more consistent with the rest of the source, and allows us to use the name more appropriately for a new variable in a later patch. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Fix NPU/PHY0/PHY1 stack orderReza Arbab1-7/+11
As previously noted in the comments, this changed in POWER9 DD2. Add a stanza reverting to the old order on DD1. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Fix indirect SCOM addressesReza Arbab2-5/+15
Change these values for POWER9 DD2, but keep backwards compatibility. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04npu2: Add a function to detect POWER9 DD1Reza Arbab1-0/+10
Provide a convenience we'll use quite a bit to preserve backwards compatibility with DD1. Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> Acked-by: Alistair Popple <alistair@popple.id.au> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-04phb4: Enable PCI peer-to-peerFrederic Barrat6-1/+168
P9 supports PCI peer-to-peer: a PCI device can write directly to the mmio space of another PCI device. It completely by-passes the CPU. It requires some configuration on the PHBs involved: 1. on the initiating side, the address for the read/write operation is in the mmio space of the target, i.e. well outside the range normally allowed. So we disable range-checking on the TVT entry in bypass mode. 2. on the target side, we need to explicitly enable p2p by setting a bit in a configuration register. It has the side-effect of reserving an outbound (as seen from the CPU) store queue for p2p. Therefore we only enable p2p on the PHBs using it, as we don't want to waste the resource if we don't have to. P9 supports p2p mmio writes. Reads are currently only supported if the two devices are under the same PHB but that is expected to change in the future, and it raises questions about intermediate switches configuration, so we report an error for the time being. The patch adds a new OPAL call to allow the OS to declare a p2p (initiator, target) pair. Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by: Russell Currey <ruscur@russell.cc> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01doc/console-log: minor updatesStewart Smith1-4/+15
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01doc: RST syntax fixesStewart Smith9-33/+52
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01doc: update copyright noticesStewart Smith1-3/+3
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01hw/npu2: fix typo in commentStewart Smith1-1/+1
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01nx: PR_INFO that NX RNG and Crypto not yet supported on POWER9Stewart Smith2-0/+8
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: tests: Move the test-miscprint to pflash testsCyril Bur7-32/+79
New code that is very much pflash functionality was added in commit f2c87a3d2f6 "pflash option to retrieve PNOR partition flags". Unfortunately at the time there wasn't an easy way to test pflash. The previous patch adds pflash infrastructure and plumbs it into `make check` nicely. This commit converts the tests originally added to libflash tests. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Add testsCyril Bur29-4/+991
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external: Consolidate Makefile.check for external toolsCyril Bur3-46/+31
The reason for this is that check targets for one tool will start to depend on other tools. For example, future pflash tests will rely on ffspart to generate pnors. The current method is too racey and results in races cleaning/building ffspart for its tests and for pflash tests. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Reinstate the progress barsCyril Bur1-16/+63
Recent work did some optimising which unfortunately removed some of the progress bars in pflash. It turns out that there's only one thing people prefer to correctly programmed flash chips, it is the ability to watch little equals characters go across their screens for potentially minutes. Personally I don't understand the appeal but I have received strongly worded requests for the reinstatement of the progress bars in pflash and I fear for the stability of our society if pflash doesn't promptly regain its most unimportant feature. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Make the progress bar safe for big numbersCyril Bur2-17/+24
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Remove use of exit() and fix memory leaksCyril Bur1-169/+213
Using exit() all over the place has lead to a huge mess of leaving all sorts of dangling references to malloc()ed memory, to blocklevel_devices and even sometimes file descriptors. Stop using exit() and simply report everything back to the main where everything can be freed on the way back out. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Move write and read size calculation togetherCyril Bur1-13/+11
Very simple rework, makes sense to calculate those at the same time. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Update the code pathes for "--tune"Cyril Bur1-3/+11
It doesn't make sense for --tune to do anything unless --direct was passed. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Remove global flash detailsCyril Bur1-59/+63
Currently all the flash details including the pointer to the blocklevel_device to access the flash is global. This is annoying since it makes it hard to know when it was allocated, some of the code just changes it which makes tracking difficult. Rather than have it globally accessible, pass it around as a structure so better control who modifies it and where and when. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Correct erase alignment checksCyril Bur1-27/+13
pflash should check the alignment of addresses and sizes when asked to erase. There are two possibilities: 1. The user has specified sizes manually in which case pflash should be as flexible as possible, blocklevel_smart_erase() permits this. To prevent possible mistakes pflash will require --force to perform a manual erase of unaligned sizes. 2. The user used -P to specify a partition, partitions aren't necessarily erase granule aligned anymore, blocklevel_smart_erase() can handle. In this it doesn't make sense to warn/error about misalignment since the misalignment is inherent to the FFS partition and not really user input. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Stop using exit() in the mainCyril Bur1-23/+49
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Check the result of strtoulCyril Bur1-8/+27
Also add 0x in front of --info output to avoid a copy and paste mistake. Reported-by: Michael Neuling <mikey@neuling.org> Suggested-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/pflash: Add description of flagsCyril Bur1-2/+4
Recent reworks of pflash expose more partition flags, the --info command only prints them in their one character short names. It isn't obvious what they all are, add a little description Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01libflash/libffs: Don't require 'part' size to be known by callersCyril Bur13-35/+37
Currently the FFS header/TOC generation code requires that consumers know the size of their TOC beforehand. While this may be advantageous in some circumstances if there are known limitations of other software. It should not be a requirement. Knowing the size of the FFS header/TOC partially breaks the abstraction since it would require consumers of the library to be aware of/have some idea of the on flash structure and size. Future work may introduce functions to force sizes but the default behaviour should be to calculate it behind the scenes. This patch also addresses an off by one issue in checking for TOC overflow. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01external/ffspart: Add .gitignoreCyril Bur1-0/+7
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01libflash/file: Break up MTD erase ioctl() callsCyril Bur1-25/+35
Unfortunately not all drivers are created equal and several drivers on which pflash relies block in the kernel for quite some time and ignore signals. This is really only a problem if pflash is to perform large erases. So don't, perform these ops in small chunks. An in kernel fix is possible in most cases but it takes time and systems will be running older drivers for quite some time. Since sector erases aren't significantly slower than whole chip erases there isn't much of a performance penalty to breaking up the erase ioctl()s. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01libflash/file: Fix bad subtraction in file erase pathCyril Bur1-1/+1
Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
2017-08-01libflash: Adding debugging outputCyril Bur6-21/+79
Also add usage text to pflash. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Reviewed-by: Samuel Mendoza-Jonas <sam@mendozajonas.com> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
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