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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-07-31 21:37:05 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-04 17:13:10 +1000 |
| commit | 7e017fa42451a23b4c332200da3db1daafe04f1e (patch) | |
| tree | bbf061bf689da6250be9661e1ddb807b14777a58 | |
| parent | d40c1a290a831301b65e2caf54f5f1104ead0eed (diff) | |
| download | skiboot-7e017fa42451a23b4c332200da3db1daafe04f1e.zip skiboot-7e017fa42451a23b4c332200da3db1daafe04f1e.tar.gz skiboot-7e017fa42451a23b4c332200da3db1daafe04f1e.tar.bz2 | |
npu2: Set the XTS config2 register
POWER9 DD2 has added a new bit we'd like to set:
"XTS_CONFIG2_NO_FLUSH_ENA:
if enabled, allows MMIO ATSDs to suppress the flush"
This has passed sanity tests with 4.12 kernels, which are capable of
exercising this capability.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Cc: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2.c | 5 | ||||
| -rw-r--r-- | include/npu2-regs.h | 1 |
2 files changed, 6 insertions, 0 deletions
@@ -784,6 +784,11 @@ static void npu2_hw_init(struct npu2 *p) val = npu2_read(p, NPU2_XTS_CFG); npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); + if (!is_p9dd1()) { + val = npu2_read(p, NPU2_XTS_CFG2); + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); + } + /* Init memory cache directory (MCD) registers. */ phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1, &gpu_min_addr, NULL); diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 73b6d62..86e2658 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -399,6 +399,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_XTS_CFG_MMIOSD PPC_BIT(1) #define NPU2_XTS_CFG_TRY_ATR_RO PPC_BIT(6) #define NPU2_XTS_CFG2 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x028) +#define NPU2_XTS_CFG2_NO_FLUSH_ENA PPC_BIT(49) #define NPU2_XTS_DBG_CFG0 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x030) #define NPU2_XTS_DBG_CFG1 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x038) #define NPU2_XTS_PMU_CNT NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x040) |