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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-07-31 21:37:00 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-04 17:13:10 +1000 |
| commit | e003ad1d7c8717d3d9d6ee40c20a68c1872d4785 (patch) | |
| tree | 2df34eddd0854113e8db88b426c526cfd6e301b0 | |
| parent | 1d086338c22048d136bdaf31ad296da471409bca (diff) | |
| download | skiboot-e003ad1d7c8717d3d9d6ee40c20a68c1872d4785.zip skiboot-e003ad1d7c8717d3d9d6ee40c20a68c1872d4785.tar.gz skiboot-e003ad1d7c8717d3d9d6ee40c20a68c1872d4785.tar.bz2 | |
npu2: Rename variable in npu2_assign_gmb()
Rename 'gmb' to 'val'. No functional change.
This is more consistent with the rest of the source, and allows us to
use the name more appropriately for a new variable in a later patch.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Acked-by: Alistair Popple <alistair@popple.id.au>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Cc: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2.c | 28 |
1 files changed, 14 insertions, 14 deletions
@@ -581,7 +581,7 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) struct npu2 *p = ndev->npu; int peers, mode; uint32_t bdfn; - uint64_t base, size, reg, gmb, old_val; + uint64_t base, size, reg, val, old_val; /* Need to work out number of link peers. This amount to * working out the maximum function number. So work start at @@ -597,15 +597,15 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) /* Base address is in GB */ base >>= 30; - gmb = SETFIELD(NPU2_MEM_BAR_SEL_MEM, 0ULL, 4); - gmb = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, gmb, base); - gmb = SETFIELD(NPU2_MEM_BAR_GROUP | NPU2_MEM_BAR_CHIP, gmb, p->chip_id); - gmb = SETFIELD(NPU2_MEM_BAR_POISON, gmb, 1); - gmb = SETFIELD(NPU2_MEM_BAR_GRANULE, gmb, 0); + val = SETFIELD(NPU2_MEM_BAR_SEL_MEM, 0ULL, 4); + val = SETFIELD(NPU2_MEM_BAR_NODE_ADDR, val, base); + val = SETFIELD(NPU2_MEM_BAR_GROUP | NPU2_MEM_BAR_CHIP, val, p->chip_id); + val = SETFIELD(NPU2_MEM_BAR_POISON, val, 1); + val = SETFIELD(NPU2_MEM_BAR_GRANULE, val, 0); /* We don't know how much memory the GPU has, so we may as well just * pass the whole aperture through at this point. */ - gmb = SETFIELD(NPU2_MEM_BAR_BAR_SIZE, gmb, ilog2(size >> 30)); + val = SETFIELD(NPU2_MEM_BAR_BAR_SIZE, val, ilog2(size >> 30)); switch (peers) { case 0: @@ -629,29 +629,29 @@ static int npu2_assign_gmb(struct npu2_dev *ndev) } mode += ndev->bdfn & 0x7; - gmb = SETFIELD(NPU2_MEM_BAR_MODE, gmb, mode); + val = SETFIELD(NPU2_MEM_BAR_MODE, val, mode); if (NPU2DEV_BRICK(ndev)) - gmb >>= 32; + val >>= 32; reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), NPU2_BLOCK_SM_0, NPU2_GPU0_MEM_BAR); old_val = npu2_read(p, reg); - gmb |= old_val; + val |= old_val; - npu2_write(p, reg, gmb); + npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), NPU2_BLOCK_SM_1, NPU2_GPU0_MEM_BAR); - npu2_write(p, reg, gmb); + npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), NPU2_BLOCK_SM_2, NPU2_GPU0_MEM_BAR); - npu2_write(p, reg, gmb); + npu2_write(p, reg, val); reg = NPU2_REG_OFFSET(NPU2_STACK_STCK_0 + NPU2DEV_STACK(ndev), NPU2_BLOCK_SM_3, NPU2_GPU0_MEM_BAR); - npu2_write(p, reg, gmb); + npu2_write(p, reg, val); return 0; } |