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2021-03-06tcg/tci: Merge mov, not and neg operationsRichard Henderson1-24/+5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge bswap operationsRichard Henderson1-18/+4
This includes bswap16 and bswap32. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge extension operationsRichard Henderson1-36/+8
This includes ext8s, ext8u, ext16s, ext16u. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge basic arithmetic operationsRichard Henderson1-54/+21
This includes add, sub, mul, and, or, xor. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Reduce use of tci_read_r64Richard Henderson1-51/+42
In all cases restricted to 64-bit hosts, tcg_read_r is identical. We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r32sRichard Henderson1-18/+2
Use explicit casts for ext32s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r32Richard Henderson1-68/+54
Use explicit casts for ext32u opcodes, and allow truncation to happen for other users. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r16sRichard Henderson1-22/+4
Use explicit casts for ext16s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r16Richard Henderson1-21/+7
Use explicit casts for ext16u opcodes, and allow truncation to happen with the store for st16 opcodes, and with the call for bswap16 opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r8sRichard Henderson1-21/+4
Use explicit casts for ext8s opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Remove tci_read_r8Richard Henderson1-18/+5
Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (load/store opcodes)Richard Henderson1-35/+14
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 5/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (conditional opcodes)Richard Henderson1-17/+6
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 4/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (deposit opcode)Richard Henderson1-10/+2
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 3/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-4-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (exchange opcodes)Richard Henderson1-21/+14
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 2/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Merge identical cases in generation (arithmetic opcodes)Richard Henderson1-48/+37
Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 1/5] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210218232840.1760806-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg: Manage splitwx in tc_ptr_to_region_tree by handRichard Henderson1-2/+18
The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg: Split out tcg_raise_tb_overflowRichard Henderson1-2/+7
Allow other places in tcg to restart with a smaller tb. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/tci: Use exec/cpu_ldst.h interfacesRichard Henderson1-45/+28
Use the provided cpu_ldst.h interfaces. This fixes the build vs the unconverted uses of g2h(), adds missed memory trace events, and correctly recognizes when a SIGSEGV belongs to the guest via set_helper_retaddr(). Fixes: 3e8f1628e864 Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/aarch64: Fix generation of "scalar" vector operationsRichard Henderson1-30/+181
For some vector operations, "1D" is not a valid type, and there are separate instructions for the 64-bit scalar operation. Tested-by: Stefan Weil <sw@weilnetz.de> Buglink: https://bugs.launchpad.net/qemu/+bug/1916112 Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/aarch64: Fix I3617_CMLE0Richard Henderson1-1/+1
Fix a typo in the encodeing of the cmle (zero) instruction. Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-06tcg/aarch64: Fix constant subtraction in tcg_out_addsub2Richard Henderson1-7/+9
An hppa guest executing 0x000000000000e05c: ldil L%10000,r4 0x000000000000e060: ldo 0(r4),r4 0x000000000000e064: sub r3,r4,sp produces ---- 000000000000e064 000000000000e068 sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0 after folding and constant propagation. Then we hit tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed. because aimm is in fact -16, but unsigned. The ((bl < 0) ^ sub) condition which negates bl is incorrect and will always lead to this abort. If the constant is positive, sub will make it negative; if the constant is negative, sub will keep it negative. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TCG_CONSTRichard Henderson4-194/+89
Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson2-10/+5
This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Restrict TCG_TARGET_NB_REGS to 16Richard Henderson2-53/+5
As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TODO as unusedRichard Henderson1-8/+0
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement 64-bit divisionRichard Henderson3-11/+25
Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*Richard Henderson2-20/+0
We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Use g_assert_not_reachedRichard Henderson1-8/+7
Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_{st_i32,st32_i64}Richard Henderson1-6/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Move stack bounds check to compile-timeRichard Henderson2-2/+13
The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_st16_{i32,i64}Richard Henderson1-7/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_st8_{i32,i64}Richard Henderson1-7/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}Richard Henderson1-6/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld16s_{i32,i64}Richard Henderson1-4/+1
Eliminating a TODO for ld16s_i64. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld16u_{i32,i64}Richard Henderson1-8/+5
Eliminating a TODO for ld16u_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld8s_{i32,i64}Richard Henderson1-8/+5
Eliminating a TODO for ld8s_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld8u_{i32,i64}Richard Henderson1-7/+13
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg64 into 64-bit callersRichard Henderson1-33/+27
Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg32 into all callersRichard Henderson1-36/+30
For a 64-bit TCI, the upper bits of a 32-bit operation are undefined (much like a native ppc64 32-bit operation). It simplifies everything if we don't force-extend the result. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg16 into the only callerRichard Henderson1-9/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg8 into its callersRichard Henderson1-7/+2
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg32s into the only callerRichard Henderson1-9/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement INDEX_op_ld8s_i64Stefan Weil1-1/+4
That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20210128020425.2055454-1-sw@weilnetz.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement INDEX_op_ld16s_i32Stefan Weil1-1/+4
That TCG opcode is used by debian-buster (arm64) running ffmpeg: qemu-aarch64 /usr/bin/ffmpeg -i theora.mkv theora.webm Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20210128024814.2056958-1-sw@weilnetz.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Make tci_tb_ptr thread-localRichard Henderson2-8/+3
Each thread must have its own pc, even under TCI. Remove the GETPC ifdef, because GETPC is always available for helpers, and thus is always required. Move the assignment under INDEX_op_call, because the value is only visible when we make a call to a helper function. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204014509.882821-6-richard.henderson@linaro.org>
2021-02-05tcg/aarch64: Do not convert TCGArg to temps that are not tempsRichard Henderson1-3/+4
Fixes INDEX_op_rotli_vec for aarch64 host, where the 3rd argument is an integer, not a temporary, which now tickles an assert added in e89b28a6350. Previously, the value computed into v2 would be garbage for rotli_vec, but as the value was unused it caused no harm. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/s390: Fix compare instruction from extended-immediate facilityPhilippe Mathieu-Daudé1-1/+1
The code is currently comparing c2 to the type promotion of uint32_t and int32_t. That is, the conversion rules are as: (common_type) c2 == (common_type) (uint32_t) (is_unsigned ? (uint32_t)c2 : (uint32_t)(int32_t)c2) In the signed case we lose the desired sign extensions because of the argument promotion rules of the ternary operator. Solve the problem by doing the round-trip parsing through the intermediate type and back to the desired common type (all at one expression). Fixes: a534bb15f30 ("tcg/s390: Use constant pool for cmpi") Tested-by: Richard W.M. Jones <rjones@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reported-by: Miroslav Rezanina <mrezanin@redhat.com> Reported-by: Richard W.M. Jones <rjones@redhat.com> Suggested-by: David Hildenbrand <david@redhat.com> Suggested-by: Eric Blake <eblake@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210204182902.1742826-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg: Remove TCG_TARGET_CON_SET_HRichard Henderson10-22/+0
All backends have now been converted to tcg-target-con-set.h, so we can remove the fallback code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-02tcg/tci: Split out constraint sets to tcg-target-con-set.hRichard Henderson3-142/+158
This requires finishing the conversion to tcg_target_op_def. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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