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14 daystcg/i386: Use vgf2p8affineqb for MO_8 vector shiftsRichard Henderson1-4/+71
A constant matrix can describe the movement of the 8 bits, so these shifts can be performed with one instruction. Logic courtesy of Andi Kleen <ak@linux.intel.com>: https://gcc.gnu.org/pipermail/gcc-patches/2025-August/691624.html Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14 daystcg/i386: Add INDEX_op_x86_vgf2p8affineqb_vecRichard Henderson2-0/+7
Add a backend-specific opcode for expanding the GFNI vgf2p8affineqb instruction, which we can use for expanding 8-bit immediate shifts and rotates. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14 daystcg/i386: Use canonical operand ordering in expand_vec_sariRichard Henderson1-2/+2
The optimizer prefers to have constants as the second operand, so expand LT x,0 instead of GT 0,x. This will not affect the generated code at all. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14 daystcg/i386: Expand sari of bits-1 as pcmpgtRichard Henderson1-0/+6
Expand arithmetic right shift of bits-1 as a comparison vs 0. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14 daystcg/arm: Fix tgen_depositRichard Henderson1-1/+2
When converting from tcg_out_deposit, the arguments were not shuffled properly. Cc: qemu-stable@nongnu.org Fixes: cf4905c03135f1181e8 ("tcg: Convert deposit to TCGOutOpDeposit") Reported-by: Michael Tokarev <mjt@tls.msk.ru> Tested-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-08-30tcg: Add tcg_gen_atomic_{xchg,fetch_and,fetch_or}_i128Richard Henderson1-3/+94
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250815122653.701782-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-21tcg/optimize: Don't fold INDEX_op_and_vec to extractRichard Henderson1-1/+1
There is no such thing as vector extract. Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-11tcg: Use uintptr_t in tcg_malloc implementationRichard Henderson1-4/+5
Avoid ubsan failure with clang-20, tcg.h:715:19: runtime error: applying non-zero offset 64 to null pointer by not using pointers. Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg: Fix constant propagation in tcg_reg_alloc_dupRichard Henderson1-1/+1
The scalar constant must be replicated for dup. Cc: qemu-stable@nongnu.org Fixes: bab1671f0fa ("tcg: Manually expand INDEX_op_dup_vec") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3002 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/riscv: Fix typo in tgen_extractRichard Henderson1-1/+1
Fix the direction of the shift, introduced when converting the codebase to TCGOutOp* and small tgen_* helpers. Fixes: 5a4d034f3cb ("tcg: Convert extract to TCGOutOpExtract") Reported-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Andrea Bolognani <abologna@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-06-30tcg/optimize: Simplify fold_eqv constant checksRichard Henderson1-3/+1
Both cases are handled by fold_xor after conversion. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Simplify fold_orc constant checksRichard Henderson1-5/+5
If operand 2 is constant, then the computation of z_mask and a_mask will produce the same results as the explicit check via fold_xi_to_i. Shift the calls of fold_xx_to_i and fold_ix_to_not down below the i2->is_const check. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Simplify fold_andc constant checksRichard Henderson1-4/+5
If operand 2 is constant, then the computation of z_mask and a_mask will produce the same results as the explicit check via fold_xi_to_i. Shift the calls of fold_xx_to_i and fold_ix_to_not down below the i2->is_const check. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Simplify fold_and constant checksRichard Henderson1-4/+3
If operand 2 is constant, then the computation of z_mask and a_mask will produce the same results as the explicit checks via fold_xi_to_i and fold_xi_to_x. Shift the call of fold_xx_to_x down below the ti_is_const(t2) check. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Fold and to extract during optimizeRichard Henderson1-3/+30
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Use fold_and in do_constant_folding_cond[12]Richard Henderson1-0/+5
When lowering tst comparisons, completely fold the and opcode that we generate. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_shiftRichard Henderson1-2/+4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_sextractRichard Henderson1-24/+6
This was the last use of fold_affected_mask, now fully replaced by fold_masks_zosa. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_movcondRichard Henderson1-2/+3
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_extuRichard Henderson1-3/+9
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_extsRichard Henderson1-2/+4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use z_bits and o_bits in fold_extract2Richard Henderson1-13/+25
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_extractRichard Henderson1-7/+5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_depositRichard Henderson1-2/+4
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_bswapRichard Henderson1-25/+24
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_xorRichard Henderson1-3/+6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use zero, one and affected bits in fold_orcRichard Henderson1-2/+9
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use one and affected bits in fold_orRichard Henderson1-2/+8
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use z_bits and o_bits in fold_notRichard Henderson1-1/+5
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use z_bits and o_bits in fold_norRichard Henderson1-4/+10
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use z_bits and o_bits in fold_nandRichard Henderson1-4/+10
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use z_bits and o_bits in fold_eqvRichard Henderson1-2/+12
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_andcRichard Henderson1-15/+8
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Build and use o_bits in fold_andRichard Henderson1-13/+7
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Introduce fold_masks_zosaRichard Henderson1-5/+11
Add a new function with an affected mask. This will allow folding to a constant to happen before folding to a copy, without having to mind the ordering in all users. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Add one's mask to TempOptInfoRichard Henderson1-16/+35
Add o_mask mirroring z_mask, but for 1's instead of 0's. Drop is_const and val fields, which now logically overlap. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-30tcg/optimize: Introduce arg_const_valRichard Henderson1-37/+41
Use arg_const_val instead of direct access to the TempOptInfo val member. Rename both val and is_const to catch all direct accesses. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Split out tcg_gen_gvec_dup_imm_varRichard Henderson1-2/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Split out tcg_gen_gvec_{add,sub}_varRichard Henderson1-6/+26
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Split out tcg_gen_gvec_mov_varRichard Henderson1-6/+15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Split out tcg_gen_gvec_3_varRichard Henderson1-38/+64
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Split out tcg_gen_gvec_2_varRichard Henderson1-32/+53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Add base arguments to check_overlap_[234]Richard Henderson1-25/+36
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Add dbase argument to expand_clrRichard Henderson1-18/+18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Add dbase argument to do_dupRichard Henderson1-16/+17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-06-23tcg: Add dbase argument to do_dup_storeRichard Henderson1-8/+8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-30Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi1-2/+2
* target/i386/kvm: Intel TDX support * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz # ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x # Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 # A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW # BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ # Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== # =XmkU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 May 2025 03:05:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) target/i386/tcg/helper-tcg: fix file references in comments target/i386: Add support for EPYC-Turin model target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits rust: make declaration of dependent crates more consistent docs: Add TDX documentation i386/tdx: Validate phys_bits against host value i386/tdx: Make invtsc default on i386/tdx: Don't treat SYSCALL as unavailable i386/tdx: Fetch and validate CPUID of TD guest target/i386: Print CPUID subleaf info for unsupported feature i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386/cgs: Introduce x86_confidential_guest_check_features() i386/tdx: Define supported KVM features for TDX i386/tdx: Add XFD to supported bit of TDX i386/tdx: Add supported CPUID bits relates to XFAM i386/tdx: Add supported CPUID bits related to TD Attributes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-28tcg: Drop TCGContext.page_{mask,bits}Richard Henderson12-29/+31
Use exec/target_page.h instead of independent variables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28tcg: Drop TCGContext.tlb_dyn_max_bitsRichard Henderson2-9/+3
This was an extremely minor optimization for aarch64 and x86_64, to use a 32-bit AND instruction when the guest softmmu tlb maximum was sufficiently small. Both hosts can simply use a 64-bit AND insn instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-26meson: remove lib{system, user}_ss aliasesPierrick Bouvier1-2/+2
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250521223414.248276-7-pierrick.bouvier@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-09-18 00:04:51 +0000