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authorRichard Henderson <richard.henderson@linaro.org>2021-01-27 20:17:49 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-02-05 10:24:14 -1000
commit7abd007cbc145c1f3745c6b1ca0deea2ef5c8591 (patch)
tree76ea7ec6ae72597795327dc928aa2ec737f55d1f /tcg
parentf6996f99f3d583d7811097368814acd0e5d4bee9 (diff)
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tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*
We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/tci.c12
-rw-r--r--tcg/tci/tcg-target.c.inc8
2 files changed, 0 insertions, 20 deletions
diff --git a/tcg/tci.c b/tcg/tci.c
index 36d5946..2532934 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -652,7 +652,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_ri32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
-#if TCG_TARGET_HAS_div_i32
case INDEX_op_div_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
@@ -677,12 +676,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t2 = tci_read_ri32(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 % t2);
break;
-#elif TCG_TARGET_HAS_div2_i32
- case INDEX_op_div2_i32:
- case INDEX_op_divu2_i32:
- TODO();
- break;
-#endif
case INDEX_op_and_i32:
t0 = *tb_ptr++;
t1 = tci_read_ri32(regs, &tb_ptr);
@@ -908,11 +901,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_remu_i64:
TODO();
break;
-#elif TCG_TARGET_HAS_div2_i64
- case INDEX_op_div2_i64:
- case INDEX_op_divu2_i64:
- TODO();
- break;
#endif
case INDEX_op_and_i64:
t0 = *tb_ptr++;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 82efb9a..6dc5bac 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -596,10 +596,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
TODO();
break;
- case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
- case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
- TODO();
- break;
case INDEX_op_brcond_i64:
tcg_out_r(s, args[0]);
tcg_out_ri64(s, const_args[1], args[1]);
@@ -639,10 +635,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_ri32(s, const_args[1], args[1]);
tcg_out_ri32(s, const_args[2], args[2]);
break;
- case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
- case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
- TODO();
- break;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32: