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2024-09-24tcg/loongarch64: remove break after g_assert_not_reached()Pierrick Bouvier1-1/+0
2024-06-19tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointersRichard Henderson1-17/+15
2024-06-19tcg/loongarch64: Enable v256 with LASXRichard Henderson2-1/+4
2024-06-19tcg/loongarch64: Support LASX in tcg_out_vec_opRichard Henderson1-84/+135
2024-06-19tcg/loongarch64: Split out vdvjukN in tcg_out_vec_opRichard Henderson1-25/+31
2024-06-19tcg/loongarch64: Remove temp_vec from tcg_out_vec_opRichard Henderson1-5/+4
2024-06-19tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st}Richard Henderson1-0/+19
2024-06-19tcg/loongarch64: Split out vdvjvk in tcg_out_vec_opRichard Henderson1-56/+63
2024-06-19tcg/loongarch64: Support LASX in tcg_out_addsub_vecRichard Henderson1-16/+20
2024-06-19tcg/loongarch64: Simplify tcg_out_addsub_vecRichard Henderson1-14/+15
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupi_vecRichard Henderson1-1/+6
2024-06-19tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vecRichard Henderson1-17/+1
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupm_vecRichard Henderson1-6/+24
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dup_vecRichard Henderson1-3/+7
2024-06-19tcg/loongarch64: Simplify tcg_out_dup_vecRichard Henderson1-16/+6
2024-06-19tcg/loongarch64: Support TCG_TYPE_V64Richard Henderson2-3/+7
2024-06-19tcg/loongarch64: Handle i32 and i64 moves between gr and frRichard Henderson1-5/+17
2024-06-19tcg/loongarch64: Use fp load/store for I32 and I64 into vector regsRichard Henderson1-26/+10
2024-06-19tcg/loongarch64: Import LASX, FP insnsRichard Henderson1-3542/+1607
2024-05-22tcg: Introduce TCG_TARGET_HAS_tst_vecRichard Henderson1-0/+1
2024-05-15tcg/loongarch64: Fill out tcg_out_{ld,st} for vector regsRichard Henderson1-23/+80
2024-02-03tcg: Add TCGConst argument to tcg_target_const_matchRichard Henderson1-1/+2
2024-02-03tcg: Introduce TCG_TARGET_HAS_tstRichard Henderson1-0/+2
2024-02-03tcg/loongarch64: Set vector registers call clobberedRichard Henderson1-1/+1
2023-11-21tcg/loongarch64: Fix tcg_out_mov() AbortedSong Gao1-0/+3
2023-11-06tcg: Remove TCG_TARGET_HAS_neg_{i32,i64}Richard Henderson1-2/+0
2023-11-06tcg/loongarch64: Implement neg opcodesRichard Henderson2-2/+11
2023-11-06tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64}Richard Henderson1-2/+0
2023-11-06tcg/loongarch64: Use cpuinfo.hRichard Henderson2-11/+5
2023-11-06tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128Richard Henderson2-7/+12
2023-10-22tcg/loongarch64: Use tcg_use_softmmuRichard Henderson1-65/+61
2023-10-07tcg: Correct invalid mentions of 'softmmu' by 'system-mode'Philippe Mathieu-Daudé1-2/+2
2023-10-04tcg/loongarch64: Fix buid errorgaosong1-33/+35
2023-09-16tcg: Add tcg_out_tb_start backend hookRichard Henderson1-0/+5
2023-09-16tcg/loongarch64: Implement 128-bit load & storeJiajie Chen3-1/+62
2023-09-15tcg/loongarch64: Lower rotli_vec to vrotriJiajie Chen2-1/+22
2023-09-15tcg/loongarch64: Lower rotv_vec ops to LSXJiajie Chen2-1/+15
2023-09-15tcg/loongarch64: Lower vector shift integer opsJiajie Chen2-1/+22
2023-09-15tcg/loongarch64: Lower bitsel_vec to vbitselJiajie Chen3-2/+12
2023-09-15tcg/loongarch64: Lower vector shift vector opsJiajie Chen2-1/+25
2023-09-15tcg/loongarch64: Lower vector saturated opsJiajie Chen2-1/+33
2023-09-15tcg/loongarch64: Lower vector min max opsJiajie Chen2-1/+33
2023-09-15tcg/loongarch64: Lower mul_vec to vmulJiajie Chen2-1/+9
2023-09-15tcg/loongarch64: Lower neg_vec to vnegJiajie Chen2-1/+9
2023-09-15tcg/loongarch64: Lower vector bitwise operationsJiajie Chen3-4/+50
2023-09-15tcg/loongarch64: Lower add/sub_vec to vadd/vsubJiajie Chen3-0/+63
2023-09-15tcg/loongarch64: Lower cmp_vec to vseq/vsle/vsltJiajie Chen3-0/+67
2023-09-15tcg: pass vece to tcg_target_const_match()Jiajie Chen1-1/+1
2023-09-15tcg/loongarch64: Lower basic tcg vec ops to LSXJiajie Chen5-2/+270
2023-09-15tcg/loongarch64: Import LSX instructionsJiajie Chen1-1/+6018
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